URL https://opencores.org/ocsvn/uart_observer/uart_observer/trunk

Subversion Repositories uart_observer

[/] [uart_observer/] [trunk/] [verilog/] [uart_receiver.v] - Diff between revs 4 and 5

Rev 4	Rev 5
Line 25...	Line 25...
`reg [7:0] mem [RAM_LENGTH - 1:0];`	`reg [7:0] mem [RAM_LENGTH - 1:0];`
`// RAM index of value currently being sent`	`// RAM index of value currently being sent`
`reg [7:0] ram_addr = 0;`	`reg [7:0] ram_addr = 0;`

`// Divider to 1 baud, receiver`	`// Divider to 1 baud, receiver`
`reg [BITS:0] divider_rx = 0;`	`reg [31:0] divider_rx = 0;`

`// Previous value of the RX line, for edge detection`	`// Previous value of the RX line, for edge detection`
`reg prev_rx = 1;`	`reg prev_rx = 1;`

`// Internal phase counters to track what we are doing`	`// Internal phase counters to track what we are doing`