URL https://opencores.org/ocsvn/usb_fpga_1_15/usb_fpga_1_15/trunk

Subversion Repositories usb_fpga_1_15

[/] [usb_fpga_1_15/] [trunk/] [include/] [ztex-fpga3.h] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 38...	Line 38...
`IFCONFIG = bmBIT7;`	`IFCONFIG = bmBIT7;`
`SYNCDELAY;`	`SYNCDELAY;`
`PORTACFG = 0;`	`PORTACFG = 0;`
`PORTCCFG = 0;`	`PORTCCFG = 0;`

`OEA = (OEA & 5 ) \| bmBIT1 \| bmBIT3 \| bmBIT4 \| bmBIT5 \| bmBIT6 \| bmBIT7;`	`OEA = bmBIT1 \| bmBIT3 \| bmBIT4 \| bmBIT5 \| bmBIT6 \| bmBIT7;`
`IOA = bmBIT7 \| mode;`	`IOA = bmBIT7 \| mode;`
`wait(10);`	`wait(10);`

`OEC &= ~bmBIT3;`	`OEC &= ~bmBIT3;`

Line 233...	Line 233...
`010003$:`	`010003$:`
`cjne r5,#0x00,010002$ // 4`	`cjne r5,#0x00,010002$ // 4`
`cjne r6,#0x00,010002$`	`cjne r6,#0x00,010002$`
`pop _OED`	`pop _OED`
`ret`	`ret`
`010002$: // approx 73 cycles per byte`	`010002$: // approx 69*4 cycles per byte`
`setb _IOA3 // 2`	`setb _IOA3 // 2`
`setb _IOC6 // 2`	`setb _IOC6 // 2`
`clr _IOA3 // 2`	`clr _IOA3 // 2`
`clr _IOC6 // 2`	`clr _IOC6 // 2`

Line 281...	Line 281...
`dec r6`	`dec r6`
`sjmp 010003$`	`sjmp 010003$`
`__endasm;`	`__endasm;`
`}`	`}`

`#include[ztex-fpga-flash.h]`	`#include[ztex-fpga-flash1.h]`

`#else`	`#else`
`#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]`	`#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]`
`#define[FLASH_BITSTREAM_ENABLED][0]`	`#define[FLASH_BITSTREAM_ENABLED][0]`
`#endif`	`#endif`