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//
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//
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`include "timescale.v"
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`include "timescale.v"
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`include "usbSerialInterfaceEngine_h.v"
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`include "usbSerialInterfaceEngine_h.v"
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module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
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module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, fullSpeedBitRate);
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input [1:0] JBit;
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input [1:0] JBit;
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input [1:0] KBit;
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input [1:0] KBit;
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input [1:0] RxBitsIn;
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input [1:0] RxBitsIn;
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input RxWireActive;
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input RxWireActive;
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input clk;
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input clk;
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Line 63... |
output [7:0] RxCtrlOut;
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output [7:0] RxCtrlOut;
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output [7:0] RxDataOut;
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output [7:0] RxDataOut;
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output processRxBitRdy;
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output processRxBitRdy;
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output processRxByteWEn;
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output processRxByteWEn;
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output resumeDetected;
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output resumeDetected;
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input fullSpeedBitRate;
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wire [1:0] JBit;
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wire [1:0] JBit;
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wire [1:0] KBit;
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wire [1:0] KBit;
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wire [1:0] RxBitsIn;
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wire [1:0] RxBitsIn;
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reg [7:0] RxCtrlOut, next_RxCtrlOut;
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reg [7:0] RxCtrlOut, next_RxCtrlOut;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [3:0]RXSameBitCount, next_RXSameBitCount;
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reg [1:0]RxBits, next_RxBits;
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reg [1:0]RxBits, next_RxBits;
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reg bitStuffError, next_bitStuffError;
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reg bitStuffError, next_bitStuffError;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [1:0]oldRXBits, next_oldRXBits;
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reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
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reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
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reg [7:0]delayCnt, next_delayCnt;
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// BINARY ENCODED state machine: prRxBit
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// BINARY ENCODED state machine: prRxBit
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// State codes definitions:
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// State codes definitions:
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`define START 4'b0000
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`define START 4'b0000
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`define IDLE_FIRST_BIT 4'b0001
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`define IDLE_FIRST_BIT 4'b0001
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`define DATA_RX_ERROR_CHK_RES 4'b1010
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`define DATA_RX_ERROR_CHK_RES 4'b1010
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`define RES_END_CHK1 4'b1011
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`define RES_END_CHK1 4'b1011
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define IDLE_WAIT_PRB_RDY 4'b1100
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_WAIT_PRB_RDY 4'b1101
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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`define DATA_RX_ERROR_WAIT_RDY 4'b1110
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`define LOW_SPEED_EOP_DELAY 4'b1111
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reg [3:0] CurrState_prRxBit;
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reg [3:0] CurrState_prRxBit;
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reg [3:0] NextState_prRxBit;
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reg [3:0] NextState_prRxBit;
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// Machine: prRxBit
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// Machine: prRxBit
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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//----------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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// Next State Logic (combinatorial)
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//----------------------------------
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//----------------------------------
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always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
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always @ (*)
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begin : prRxBit_NextState
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begin : prRxBit_NextState
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NextState_prRxBit <= CurrState_prRxBit;
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NextState_prRxBit <= CurrState_prRxBit;
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// Set default values for outputs and signals
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// Set default values for outputs and signals
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next_processRxByteWEn <= processRxByteWEn;
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next_processRxByteWEn <= processRxByteWEn;
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next_RxCtrlOut <= RxCtrlOut;
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next_RxCtrlOut <= RxCtrlOut;
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next_RXBitCount <= RXBitCount;
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next_RXBitCount <= RXBitCount;
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next_oldRXBits <= oldRXBits;
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next_oldRXBits <= oldRXBits;
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next_RXByte <= RXByte;
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next_RXByte <= RXByte;
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next_bitStuffError <= bitStuffError;
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next_bitStuffError <= bitStuffError;
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next_resumeWaitCnt <= resumeWaitCnt;
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next_resumeWaitCnt <= resumeWaitCnt;
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next_delayCnt <= delayCnt;
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next_processRxBitRdy <= processRxBitRdy;
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next_processRxBitRdy <= processRxBitRdy;
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case (CurrState_prRxBit)
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case (CurrState_prRxBit)
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`START:
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`START:
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begin
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begin
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next_processRxByteWEn <= 1'b0;
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next_processRxByteWEn <= 1'b0;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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`DATA_RX_CHK_SE0:
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`DATA_RX_CHK_SE0:
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begin
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begin
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next_bitStuffError <= 1'b0;
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next_bitStuffError <= 1'b0;
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if (RxBits == `SE0)
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if (RxBits == `SE0) begin
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if (fullSpeedBitRate == 1'b0) begin
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NextState_prRxBit <= `LOW_SPEED_EOP_DELAY;
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next_delayCnt <= 8'h00;
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end
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else
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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end
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else
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else
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begin
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begin
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NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
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NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
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if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
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if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
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begin
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begin
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//clear resume detected flag
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//clear resume detected flag
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end
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end
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NextState_prRxBit <= `WAIT_BITS;
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NextState_prRxBit <= `WAIT_BITS;
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next_processRxBitRdy <= 1'b1;
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next_processRxBitRdy <= 1'b1;
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end
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end
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`LOW_SPEED_EOP_DELAY:
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begin
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//turn around time must be at least 2 low speed bit periods
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next_delayCnt <= delayCnt + 1'b1;
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if (delayCnt == `LS_OVER_SAMPLE_RATE * 2)
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NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
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end
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endcase
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endcase
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end
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end
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//----------------------------------
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//----------------------------------
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// Current State Logic (sequential)
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// Current State Logic (sequential)
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Line 391... |
RXBitCount <= 4'h0;
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RXBitCount <= 4'h0;
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oldRXBits <= 2'b00;
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oldRXBits <= 2'b00;
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RXByte <= 8'h00;
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RXByte <= 8'h00;
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bitStuffError <= 1'b0;
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bitStuffError <= 1'b0;
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resumeWaitCnt <= 5'h0;
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resumeWaitCnt <= 5'h0;
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delayCnt <= 8'h00;
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processRxByteWEn <= 1'b0;
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processRxByteWEn <= 1'b0;
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RxCtrlOut <= 8'h00;
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RxCtrlOut <= 8'h00;
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RxDataOut <= 8'h00;
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RxDataOut <= 8'h00;
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resumeDetected <= 1'b0;
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resumeDetected <= 1'b0;
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processRxBitRdy <= 1'b1;
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processRxBitRdy <= 1'b1;
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Line 408... |
RXBitCount <= next_RXBitCount;
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RXBitCount <= next_RXBitCount;
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oldRXBits <= next_oldRXBits;
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oldRXBits <= next_oldRXBits;
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RXByte <= next_RXByte;
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RXByte <= next_RXByte;
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bitStuffError <= next_bitStuffError;
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bitStuffError <= next_bitStuffError;
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resumeWaitCnt <= next_resumeWaitCnt;
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resumeWaitCnt <= next_resumeWaitCnt;
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delayCnt <= next_delayCnt;
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processRxByteWEn <= next_processRxByteWEn;
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processRxByteWEn <= next_processRxByteWEn;
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RxCtrlOut <= next_RxCtrlOut;
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RxCtrlOut <= next_RxCtrlOut;
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RxDataOut <= next_RxDataOut;
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RxDataOut <= next_RxDataOut;
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resumeDetected <= next_resumeDetected;
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resumeDetected <= next_resumeDetected;
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processRxBitRdy <= next_processRxBitRdy;
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processRxBitRdy <= next_processRxBitRdy;
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end
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end
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end
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end
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endmodule
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endmodule
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