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architecture str of usimplez_top is
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architecture str of usimplez_top is
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component usimplez_cpu
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component usimplez_cpu
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generic
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generic
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( WIDTH_DATA_BUS: natural;
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( WIDTH_WORD: natural;
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WIDTH_OPERATION_CODE: natural;
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WIDTH_OPERATION_CODE: natural;
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WIDTH_ADDRESS: natural;
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WIDTH_ADDRESS: natural;
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--Instructions:
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--Instructions:
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ST: std_logic_vector(2 downto 0);
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ST: std_logic_vector;
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LD: std_logic_vector(2 downto 0);
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LD: std_logic_vector;
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ADD: std_logic_vector(2 downto 0);
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ADD: std_logic_vector;
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BR: std_logic_vector(2 downto 0);
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BR: std_logic_vector;
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BZ: std_logic_vector(2 downto 0);
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BZ: std_logic_vector;
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CLR: std_logic_vector(2 downto 0);
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CLR: std_logic_vector;
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DEC: std_logic_vector(2 downto 0);
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DEC: std_logic_vector;
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HALT: std_logic_vector(2 downto 0)
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HALT: std_logic_vector
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);
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);
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port
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port
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( clk_i : in std_logic;
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( clk_i : in std_logic;
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rst_i : in std_logic;
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rst_i : in std_logic;
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data_bus_i : in std_logic_vector(WIDTH_DATA_BUS-1 downto 0); --here
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data_bus_i : in std_logic_vector(WIDTH_WORD-1 downto 0);
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we_o : out std_logic;
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we_o : out std_logic;
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in0_o : out std_logic;
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in0_o : out std_logic;
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in1_o : out std_logic;
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in1_o : out std_logic;
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op0_o : out std_logic;
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op0_o : out std_logic;
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op1_o : out std_logic;
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op1_o : out std_logic;
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addr_bus_o : out std_logic_vector(8 downto 0);
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addr_bus_o : out std_logic_vector(WIDTH_ADDRESS-1 downto 0);
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data_bus_o : out std_logic_vector(11 downto 0)
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data_bus_o : out std_logic_vector(WIDTH_WORD-1 downto 0)
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);
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);
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end component;
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end component;
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component usimplez_ram
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component usimplez_ram
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generic
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generic
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WIDTH_WORD : natural
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WIDTH_WORD : natural
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);
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);
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port
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port
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( clk_i : in std_logic;
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( clk_i : in std_logic;
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we_i : in std_logic;
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we_i : in std_logic;
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addr_i : in std_logic_vector(8 downto 0);
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addr_i : in std_logic_vector(WIDTH_ADDRESS-1 downto 0);
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data_i : in std_logic_vector(11 downto 0);
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data_i : in std_logic_vector(WIDTH_WORD-1 downto 0);
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data_o : out std_logic_vector(11 downto 0)
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data_o : out std_logic_vector(WIDTH_WORD-1 downto 0)
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);
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);
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end component;
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end component;
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signal rd_data_bus_s : std_logic_vector(WIDTH_WORD-1 downto 0);
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signal rd_data_bus_s : std_logic_vector(WIDTH_WORD-1 downto 0);
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signal we_s : std_logic;
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signal we_s : std_logic;
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we_o <= we_s;
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we_o <= we_s;
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cpu:usimplez_cpu
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cpu:usimplez_cpu
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generic map
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generic map
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( WIDTH_DATA_BUS => 12,
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( WIDTH_WORD => 12,
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WIDTH_ADDRESS => 9,
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WIDTH_ADDRESS => 9,
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WIDTH_OPERATION_CODE => 3,
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WIDTH_OPERATION_CODE => 3,
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ST => "000",
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ST => "000",
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LD => "001",
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LD => "001",
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ADD => "010",
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ADD => "010",
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