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[/] [usimplez/] [trunk/] [QuartusII/] [usimplez_top.vwf] - Diff between revs 2 and 3

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Rev 2 Rev 3
Line 30... Line 30...
        GRID_PHASE = 0.0;
        GRID_PHASE = 0.0;
        GRID_PERIOD = 10.0;
        GRID_PERIOD = 10.0;
        GRID_DUTY_CYCLE = 50;
        GRID_DUTY_CYCLE = 50;
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador")
SIGNAL("clk_i")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = INPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("in0_o")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = OUTPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("in1_o")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = OUTPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("op0_o")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = OUTPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("op1_o")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = OUTPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("rst_i")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = INPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("we_o")
 
{
 
        VALUE_TYPE = NINE_LEVEL_BIT;
 
        SIGNAL_TYPE = SINGLE_BIT;
 
        WIDTH = 1;
 
        LSB_INDEX = -1;
 
        DIRECTION = OUTPUT;
 
        PARENT = "";
 
}
 
 
 
SIGNAL("usimplez_cpu:cpu|ac_reg_s")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = BUS;
        SIGNAL_TYPE = BUS;
        WIDTH = 12;
        WIDTH = 12;
        LSB_INDEX = 0;
        LSB_INDEX = 0;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "";
        PARENT = "";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[11]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[11]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[10]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[10]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[9]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[9]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[8]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[8]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[7]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[7]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[6]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[6]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[5]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[5]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[4]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[4]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[3]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[3]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[2]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[2]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[1]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[1]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|acumulador[0]")
SIGNAL("usimplez_cpu:cpu|ac_reg_s[0]")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        SIGNAL_TYPE = SINGLE_BIT;
        WIDTH = 1;
        WIDTH = 1;
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|acumulador";
        PARENT = "usimplez_cpu:cpu|ac_reg_s";
}
}
 
 
SIGNAL("usimplez_cpu:cpu|addr_bus_o")
SIGNAL("usimplez_cpu:cpu|addr_bus_o")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        VALUE_TYPE = NINE_LEVEL_BIT;
Line 630... Line 700...
        LSB_INDEX = -1;
        LSB_INDEX = -1;
        DIRECTION = REGISTERED;
        DIRECTION = REGISTERED;
        PARENT = "usimplez_cpu:cpu|data_bus_o";
        PARENT = "usimplez_cpu:cpu|data_bus_o";
}
}
 
 
SIGNAL("clk_i")
TRANSITION_LIST("clk_i")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                NODE
        DIRECTION = INPUT;
                {
        PARENT = "";
                        REPEAT = 2000;
 
                        LEVEL 0 FOR 25.0;
 
                        LEVEL 1 FOR 25.0;
 
                }
 
        }
}
}
 
 
SIGNAL("in0_o")
TRANSITION_LIST("in0_o")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                LEVEL X FOR 100000.0;
        DIRECTION = OUTPUT;
        }
        PARENT = "";
 
}
}
 
 
SIGNAL("in1_o")
TRANSITION_LIST("in1_o")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                LEVEL X FOR 100000.0;
        DIRECTION = OUTPUT;
        }
        PARENT = "";
 
}
}
 
 
SIGNAL("op0_o")
TRANSITION_LIST("op0_o")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                LEVEL X FOR 100000.0;
        DIRECTION = OUTPUT;
        }
        PARENT = "";
 
}
}
 
 
SIGNAL("op1_o")
TRANSITION_LIST("op1_o")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                LEVEL X FOR 100000.0;
        DIRECTION = OUTPUT;
        }
        PARENT = "";
 
}
}
 
 
SIGNAL("rst_i")
TRANSITION_LIST("rst_i")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                LEVEL 0 FOR 4.0;
        DIRECTION = INPUT;
                LEVEL 1 FOR 12.8;
        PARENT = "";
                LEVEL 0 FOR 99983.2;
 
        }
}
}
 
 
SIGNAL("we_o")
TRANSITION_LIST("we_o")
{
{
        VALUE_TYPE = NINE_LEVEL_BIT;
        NODE
        SIGNAL_TYPE = SINGLE_BIT;
        {
        WIDTH = 1;
                REPEAT = 1;
        LSB_INDEX = -1;
                LEVEL X FOR 100000.0;
        DIRECTION = OUTPUT;
        }
        PARENT = "";
 
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[11]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[11]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[10]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[10]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[9]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[9]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[8]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[8]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[7]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[7]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[6]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[6]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[5]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[5]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[4]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[4]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[3]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[3]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[2]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[2]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[1]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[1]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("usimplez_cpu:cpu|acumulador[0]")
TRANSITION_LIST("usimplez_cpu:cpu|ac_reg_s[0]")
{
{
        NODE
        NODE
        {
        {
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
Line 1186... Line 1256...
                REPEAT = 1;
                REPEAT = 1;
                LEVEL U FOR 100000.0;
                LEVEL U FOR 100000.0;
        }
        }
}
}
 
 
TRANSITION_LIST("clk_i")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                NODE
 
                {
 
                        REPEAT = 2000;
 
                        LEVEL 0 FOR 25.0;
 
                        LEVEL 1 FOR 25.0;
 
                }
 
        }
 
}
 
 
 
TRANSITION_LIST("in0_o")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                LEVEL X FOR 100000.0;
 
        }
 
}
 
 
 
TRANSITION_LIST("in1_o")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                LEVEL X FOR 100000.0;
 
        }
 
}
 
 
 
TRANSITION_LIST("op0_o")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                LEVEL X FOR 100000.0;
 
        }
 
}
 
 
 
TRANSITION_LIST("op1_o")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                LEVEL X FOR 100000.0;
 
        }
 
}
 
 
 
TRANSITION_LIST("rst_i")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                LEVEL 0 FOR 4.0;
 
                LEVEL 1 FOR 11.6;
 
                LEVEL 0 FOR 99984.4;
 
        }
 
}
 
 
 
TRANSITION_LIST("we_o")
 
{
 
        NODE
 
        {
 
                REPEAT = 1;
 
                LEVEL X FOR 100000.0;
 
        }
 
}
 
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "rst_i";
        CHANNEL = "rst_i";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
Line 1276... Line 1276...
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "we_o";
        CHANNEL = "in0_o";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 2;
        TREE_INDEX = 2;
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "in0_o";
        CHANNEL = "in1_o";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 3;
        TREE_INDEX = 3;
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "in1_o";
        CHANNEL = "op0_o";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 4;
        TREE_INDEX = 4;
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "op0_o";
        CHANNEL = "op1_o";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 5;
        TREE_INDEX = 5;
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "op1_o";
        CHANNEL = "we_o";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 6;
        TREE_INDEX = 6;
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 7;
        TREE_INDEX = 7;
        TREE_LEVEL = 0;
        TREE_LEVEL = 0;
        CHILDREN = 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19;
        CHILDREN = 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[11]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[11]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 8;
        TREE_INDEX = 8;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[10]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[10]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 9;
        TREE_INDEX = 9;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[9]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[9]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 10;
        TREE_INDEX = 10;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[8]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[8]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 11;
        TREE_INDEX = 11;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[7]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[7]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 12;
        TREE_INDEX = 12;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[6]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[6]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 13;
        TREE_INDEX = 13;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[5]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[5]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 14;
        TREE_INDEX = 14;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[4]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[4]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 15;
        TREE_INDEX = 15;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[3]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[3]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 16;
        TREE_INDEX = 16;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[2]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[2]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 17;
        TREE_INDEX = 17;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[1]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[1]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 18;
        TREE_INDEX = 18;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
}
}
 
 
DISPLAY_LINE
DISPLAY_LINE
{
{
        CHANNEL = "usimplez_cpu:cpu|acumulador[0]";
        CHANNEL = "usimplez_cpu:cpu|ac_reg_s[0]";
        EXPAND_STATUS = COLLAPSED;
        EXPAND_STATUS = COLLAPSED;
        RADIX = Unsigned;
        RADIX = Unsigned;
        TREE_INDEX = 19;
        TREE_INDEX = 19;
        TREE_LEVEL = 1;
        TREE_LEVEL = 1;
        PARENT = 7;
        PARENT = 7;
Line 1921... Line 1921...
        PARENT = 54;
        PARENT = 54;
}
}
 
 
TIME_BAR
TIME_BAR
{
{
        TIME = 9575;
        TIME = 10200;
        MASTER = TRUE;
        MASTER = TRUE;
}
}
;
;

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