URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram.v] - Diff between revs 18 and 26

Rev 18	Rev 26
Line 1...	Line 1...
`// true dual port RAM, sync`	`// true dual port RAM, sync`

	`ifdef ACTEL
	`define SYN /synthesis syn_ramstyle = "no_rw_check"/
	`endif
module vfifo_dual_port_ram_`TYPE	module vfifo_dual_port_ram_`TYPE
`(`	`(`
`// A side`	`// A side`
`d_a,`	`d_a,`
`ifdef DW	`ifdef DW
Line 49...	Line 53...
`else	`else
`reg [(DATA_WIDTH-1):0] q_b;`	`reg [(DATA_WIDTH-1):0] q_b;`
`endif	`endif

`// Declare the RAM variable`	`// Declare the RAM variable`
`reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`	reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;

`ifdef DC	`ifdef DC
`always @ (posedge clk_a)`	`always @ (posedge clk_a)`
`else	`else
`always @ (posedge clk)`	`always @ (posedge clk)`