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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Diff between revs 6 and 14

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//=tab Main
//=tab Main
//=comment <b>Versatile IO</b>
//=comment <b>Versatile IO</b>
//=tab UART
//=tab UART
`define UART0
`define UART0
`define UART0_BASE_ADR 32'h92000000
`define UART0_BASE_ADR 32'h90000000
`define UART0_MEM_MAP_HI 31
`define UART0_MEM_MAP_HI 31
`define UART0_MEM_MAP_LO 24
`define UART0_MEM_MAP_LO 24
`ifdef UART0
`ifdef UART0
`define UART
`define UART
`endif
`endif

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