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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [uart16550/] [Makefile] - Diff between revs 3 and 5

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Rev 3 Rev 5
Line 1... Line 1...
SVN_PATH = http://opencores.org/ocsvn/uart16550/uart16550/trunk/rtl/verilog/
SVN_PATH = http://opencores.org/ocsvn/uart16550/uart16550/trunk/rtl/verilog/
 
 
DEFINE_FILES = uart_defines.v
#DEFINE_FILES = uart_defines.v
DEFINE_FILES += timescale.v
DEFINE_FILES = timescale.v
 
 
RTL_FILES = raminfr.v
RTL_FILES = raminfr.v
RTL_FILES += uart_debug_if.v
RTL_FILES += uart_debug_if.v
RTL_FILES += uart_receiver.v
RTL_FILES += uart_receiver.v
RTL_FILES += uart_regs.v
RTL_FILES += uart_regs.v

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