| Line 1540... |
Line 1540... |
`undef MODULE
|
`undef MODULE
|
// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
// avalon master side
|
// avalon master side
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
|
|
init_done,
|
// common
|
// common
|
clk, rst);
|
clk, rst);
|
|
|
parameter adr_width = 30;
|
parameter adr_width = 30;
|
parameter dat_width = 32;
|
parameter dat_width = 32;
|
| Line 1569... |
Line 1570... |
output write;
|
output write;
|
output read;
|
output read;
|
output beginbursttransfer;
|
output beginbursttransfer;
|
output [3:0] burstcount;
|
output [3:0] burstcount;
|
input waitrequest;
|
input waitrequest;
|
|
input init_done;
|
input clk, rst;
|
input clk, rst;
|
|
|
reg last_cyc_idle_or_eoc;
|
// cnt1 - initiated read or writes
|
|
// cnt2 - # of read or writes in pipeline
|
|
reg [3:0] cnt1;
|
|
reg [3:0] cnt1;
|
|
|
|
reg next_state, state;
|
|
localparam s0 = 1'b0;
|
|
localparam s1 = 1'b1;
|
|
|
|
wire eoc;
|
|
|
|
always @ *
|
|
begin
|
|
case (state)
|
|
s0: if (init_done & wbs_cyc_i) next_state <= s1;
|
|
s1: if (cnt2==4'h1 & )
|
|
default: next_state <= state;
|
|
end
|
|
end
|
|
|
reg [3:0] cnt;
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
cnt <= 4'h0;
|
state <= s0;
|
else
|
else
|
if (beginbursttransfer & waitrequest)
|
state <= next_state;
|
cnt <= burst_size - 1;
|
|
else if (beginbursttransfer & !waitrequest)
|
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
|
cnt <= burst_size - 2;
|
always @ (posedge clk or posedge rst)
|
else if (wbs_ack_o)
|
if (rst)
|
cnt <= cnt - 1;
|
cnt1 <= 4'h0;
|
|
else
|
|
if (read & !waitrequest & init_done)
|
|
cnt1 <= burst_size - 1;
|
|
else if (write & !waitrequest & init_done)
|
|
cnt1 <= cnt1 + 4'h1;
|
|
else if (next_state==idle)
|
|
cnt1 <= 4'h0;
|
|
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
cnt2 <= 4'h0;
|
|
else
|
|
if (read & !waitrequest & init_done)
|
|
cnt2 <= burst_size - 1;
|
|
else if (write & !waitrequest & init_done & )
|
|
cnt2 <= cnt1 + 4'h1;
|
|
else if (next_state==idle)
|
|
cnt2 <= 4'h0;
|
|
|
reg wr_ack;
|
reg wr_ack;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
wr_ack <= 1'b0;
|
wr_ack <= 1'b0;
|
| Line 1596... |
Line 1633... |
|
|
// to avalon
|
// to avalon
|
assign writedata = wbs_dat_i;
|
assign writedata = wbs_dat_i;
|
assign address = wbs_adr_i;
|
assign address = wbs_adr_i;
|
assign be = wbs_sel_i;
|
assign be = wbs_sel_i;
|
assign write = cnt==(burst_size-1) & wbs_cyc_i & wbs_we_i;
|
assign write = cnt!=4'h0 & wbs_cyc_i & wbs_we_i;
|
assign read = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
|
assign read = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
|
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
|
assign beginbursttransfer = state==s0 & next_state==s1;
|
assign burstcount = burst_size;
|
assign burstcount = burst_size;
|
|
|
// to wishbone
|
// to wishbone
|
assign wbs_dat_o = readdata;
|
assign wbs_dat_o = readdata;
|
assign wbs_ack_o = wr_ack | readdatavalid;
|
assign wbs_ack_o = wr_ack | readdatavalid;
|
