URL
https://opencores.org/ocsvn/viterbi_decoder_axi4s/viterbi_decoder_axi4s/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 2 |
Rev 4 |
| Line 28... |
Line 28... |
generic(
|
generic(
|
CLK_PERIOD : time := 10 ns; -- Clock period within simulation.
|
CLK_PERIOD : time := 10 ns; -- Clock period within simulation.
|
|
|
BLOCK_LENGTH_START : natural := 200; -- First block length to simulate.
|
BLOCK_LENGTH_START : natural := 200; -- First block length to simulate.
|
BLOCK_LENGTH_END : natural := 300; -- Last block length to simulate.
|
BLOCK_LENGTH_END : natural := 300; -- Last block length to simulate.
|
BLOCK_LENGTH_INCR : integer := 20; -- Increment from one block length to another.
|
BLOCK_LENGTH_INCR : integer := 100; -- Increment from one block length to another.
|
|
|
SIM_ALL_BLOCKS : boolean := true; -- Set to true in order to simulate all blocks within a data file.
|
SIM_ALL_BLOCKS : boolean := true; -- Set to true in order to simulate all blocks within a data file.
|
SIM_BLOCK_START : natural := 396; -- If SIM_ALL_BLOCKS = false, gives block to start simulation with.
|
SIM_BLOCK_START : natural := 396; -- If SIM_ALL_BLOCKS = false, gives block to start simulation with.
|
SIM_BLOCK_END : natural := 398; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.
|
SIM_BLOCK_END : natural := 398; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.