URL https://opencores.org/ocsvn/viterbi_decoder_axi4s/viterbi_decoder_axi4s/trunk

Subversion Repositories viterbi_decoder_axi4s

[/] [viterbi_decoder_axi4s/] [trunk/] [testbench/] [tb_dec_viterbi.vhd] - Diff between revs 4 and 5

Rev 4	Rev 5
Line 37...	Line 37...
`SIM_BLOCK_END : natural := 398; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.`	`SIM_BLOCK_END : natural := 398; -- If SIM_ALL_BLOCKS = false, gives last block of simulation.`

`WINDOW_LENGTH : natural := 55; -- Window length to use for simulation.`	`WINDOW_LENGTH : natural := 55; -- Window length to use for simulation.`
`ACQUISITION_LENGTH : natural := 50; -- Acquisition length to use for simulation.`	`ACQUISITION_LENGTH : natural := 50; -- Acquisition length to use for simulation.`

`DATA_DIRECTORY : string := "../testbench/" -- Path to testbench data, relative to simulation directory.`	`DATA_DIRECTORY : string := "../testbench/WiFi_121_91/" -- Path to testbench data, relative to simulation directory.`
`);`	`);`
`end entity tb_dec_viterbi;`	`end entity tb_dec_viterbi;`


`architecture sim of tb_dec_viterbi is`	`architecture sim of tb_dec_viterbi is`