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\documentclass{gqtekspec}
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\documentclass{gqtekspec}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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%% Filename: spec.tex
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%% Filename: spec.tex
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%%
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%%
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%% Project:
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%% Project: Pipelined Wishbone to AXI coverter
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%%
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%%
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%% Purpose:
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%% Purpose: This document is a LaTeX description describing how to build
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%% a specification document for the cores within this Pipelined
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%% WB2AXI repository.
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%%
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%%
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%% Creator:
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%% Creator: Dan Gisselquist, Ph.D.
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%% Gisselquist Technology, LLC
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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%% Copyright (C) 2018, Gisselquist Technology, LLC
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%%
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%% This program is free software (firmware): you can redistribute it and/or
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%% modify it under the terms of the GNU General Public License as published
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%% by the Free Software Foundation, either version 3 of the License, or (at
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%% your option) any later version.
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%%
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%% This program is distributed in the hope that it will be useful, but WITHOUT
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%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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%% for more details.
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%%
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%% You should have received a copy of the GNU General Public License along
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%% with this program. (It's in the $(ROOT)/doc directory, run make with no
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%% target there if the PDF file isn't present.) If not, see
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%% <http://www.gnu.org/licenses/> for a copy.
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%%
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%% License: GPL, v3, as defined and found on www.gnu.org,
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%% http://www.gnu.org/licenses/gpl.html
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%%
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%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%
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%%
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\usepackage{import}
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\usepackage{import}
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\usepackage{bytefield}
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\usepackage{bytefield}
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\project{Wishbone to AXI}
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\project{Wishbone to AXI}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{zipcpu (at) gmail.com}
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\revision{Rev.~0.0}
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\revision{Rev.~0.1}
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\begin{document}
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\begin{document}
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\pagestyle{gqtekspecplain}
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\pagestyle{gqtekspecplain}
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\titlepage
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\titlepage
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\begin{license}
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\begin{license}
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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Copyright (C) \theyear\today, Gisselquist Technology, LLC
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This project is free software (firmware): you can redistribute it and/or
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This project is free software (firmware): you can redistribute it and/or
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modify it under the terms of the GNU General Public License as published
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modify it under the terms of the GNU General Public License as published
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by the Free Software Foundation, either version 3 of the License, or (at
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by the Free Software Foundation, either version 3 of the License, or (at
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your option) any later version.
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your option) any later version.
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Some files within this repository have been released under the GNU Lesser
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General Public License. These components may be separated from this repository,
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and redistributed or modified under the terms of the Lesser GNU
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Public License, again as published by the Free Software Foundation,
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either vversion 3 of the License or (at your option) any later
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version. These files will identified as such in their headers.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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for more details, or the GNU Lesser General Public License as appropriate.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of both the GNU General Public License as
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with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
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well as the GNU Lesser General Public License along with this repository.
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(They are both in the \$(ROOT)/doc directory. Run make with no target there
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if the PDF files are not present.) If not, see If not, see
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\texttt{http://www.gnu.org/licenses/} for a copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.0 & 9/6/2016 & D. Gisselquist & First draft\\\hline
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0.0 & 9/6/2016 & D. Gisselquist & First draft\\\hline
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\end{revisionhistory}
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\end{revisionhistory}
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% Revision History
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% Revision History
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% Table of Contents, named Contents
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% Table of Contents, named Contents
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\tableofcontents
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\tableofcontents
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\listoffigures
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\listoffigures
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\listoftables
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\listoftables
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\begin{preface}
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\begin{preface}
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This controller is born of necessity. As long as Xilinx's proprietary IP
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The wishbone to AXI controller is born of necessity. As long as Xilinx's
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makes it difficult to access memory, providing only access via the proprietary
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proprietary IP makes it difficult to access memory, providing only access
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AXI bus, some conversion will be necessary for anyone who wishes to use a
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via the proprietary AXI bus, some conversion will be necessary for anyone
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wishbone interface.
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who wishes to use a wishbone interface.
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A special shout out and thanks go to Stephan Wallentowitz, for his first
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A special shout out and thanks go to Stephan Wallentowitz, for his first
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draft of such a converter, and to Olofk for encouraging me to write it.
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draft of such a converter, and to Olofk for encouraging me to write this
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initial core.
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The project has since grown into a general purpose set of both bus bridges
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and formal bus properties, to include support for Wishbone, AXI-lite, and
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Avalon busses. The full AXI implementation, together with the bridges
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between full AXI and other busses, remains a work in progress.
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\end{preface}
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\end{preface}
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\chapter{Introduction}\label{ch:intro}
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\chapter{Introduction}\label{ch:intro}
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\pagenumbering{arabic}
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\pagenumbering{arabic}
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\setcounter{page}{1}
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\setcounter{page}{1}
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\begin{table}[htbp]
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\begin{table}[htbp]
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\begin{center}
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\begin{center}
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\begin{wishboneds}
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\begin{wishboneds}
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Revision level of wishbone & WB B4 spec \\\hline
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Revision level of wishbone & WB B4 spec \\\hline
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Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
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Type of interface & Slave, Read/Write, pipeline reads supported \\\hline
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Port size & 128--bit or 32--bit \\\hline
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Port size & Various and configurable \\\hline
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Port granularity & 8--bit \\\hline
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Port granularity & 8--bit \\\hline
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Maximum Operand Size & 128--bit or 32--bit \\\hline
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Maximum Operand Size & Various and configurable\\\hline
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Data transfer ordering & (Preserved) \\\hline
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Data transfer ordering & (Preserved) \\\hline
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Clock constraints & None.\\\hline
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Clock constraints & None.\\\hline
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Signal Names & \begin{tabular}{ll}
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Signal Names & \begin{tabular}{ll}
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Signal Name & Wishbone Equivalent \\\hline
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Signal Name & Wishbone Equivalent \\\hline
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{\tt i\_wb\_clk} & {\tt CLK\_I} \\
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{\tt i\_wb\_clk} & {\tt CLK\_I} \\
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