| Line 4... |
Line 4... |
//
|
//
|
// Project: Pipelined Wishbone to AXI converter
|
// Project: Pipelined Wishbone to AXI converter
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//
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//
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// Purpose: This is a priority bus arbiter. It allows two separate wishbone
|
// Purpose: This is a priority bus arbiter. It allows two separate wishbone
|
// masters to connect to the same bus, while also guaranteeing
|
// masters to connect to the same bus, while also guaranteeing
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// that one master can have the bus with no delay any time the other
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// that the last master can have the bus with no delay any time it is
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// master is not using the bus. The goal is to eliminate as much
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// idle. The goal is to minimize the combinatorial logic required in this
|
// combinatorial logic as possible, while still guarateeing minimum access
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// process, while still minimizing access time.
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// time for the priority (last, or alternate) channel.
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//
|
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// The core logic works like this:
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//
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// 1. If 'A' or 'B' asserts the o_cyc line, a bus cycle will begin,
|
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// with acccess granted to whomever requested it.
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// 2. If both 'A' and 'B' assert o_cyc at the same time, only 'A'
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// will be granted the bus. (If the alternating parameter
|
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// is set, A and B will alternate who gets the bus in
|
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// this case.)
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// 3. The bus will remain owned by whomever the bus was granted to
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// until they deassert the o_cyc line.
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// 4. At the end of a bus cycle, o_cyc is guaranteed to be
|
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// deasserted (low) for one clock.
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// 5. On the next clock, bus arbitration takes place again. If
|
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// 'A' requests the bus, no matter how long 'B' was
|
|
// waiting, 'A' will then be granted the bus. (Unless
|
|
// again the alternating parameter is set, then the
|
|
// access is guaranteed to switch to B.)
|
|
//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
|
//
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//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
|
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
|
//
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//
|
// This program is free software (firmware): you can redistribute it and/or
|
// This file is part of the pipelined Wishbone to AXI converter project, a
|
// modify it under the terms of the GNU General Public License as published
|
// project that contains multiple bus bridging designs and formal bus property
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
// sets.
|
// your option) any later version.
|
//
|
//
|
// The bus bridge designs and property sets are free RTL designs: you can
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
// redistribute them and/or modify any of them under the terms of the GNU
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
// Lesser General Public License as published by the Free Software Foundation,
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
// either version 3 of the License, or (at your option) any later version.
|
// for more details.
|
//
|
//
|
// The bus bridge designs and property sets are distributed in the hope that
|
// You should have received a copy of the GNU General Public License along
|
// they will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
|
// warranty of MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
// target there if the PDF file isn't present.) If not, see
|
// GNU Lesser General Public License for more details.
|
|
//
|
|
// You should have received a copy of the GNU Lesser General Public License
|
|
// along with these designs. (It's in the $(ROOT)/doc directory. Run make
|
|
// with no target there if the PDF file isn't present.) If not, see
|
// <http://www.gnu.org/licenses/> for a copy.
|
// <http://www.gnu.org/licenses/> for a copy.
|
//
|
//
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
// License: LGPL, v3, as defined and found on www.gnu.org,
|
// http://www.gnu.org/licenses/gpl.html
|
// http://www.gnu.org/licenses/lgpl.html
|
//
|
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
`default_nettype none
|
`default_nettype none
|
| Line 50... |
Line 71... |
o_a_ack, o_a_stall, o_a_err,
|
o_a_ack, o_a_stall, o_a_err,
|
// Bus B
|
// Bus B
|
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
|
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
|
o_b_ack, o_b_stall, o_b_err,
|
o_b_ack, o_b_stall, o_b_err,
|
// Combined/arbitrated bus
|
// Combined/arbitrated bus
|
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
|
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err
|
|
`ifdef FORMAL
|
|
,
|
|
f_a_nreqs, f_a_nacks, f_a_outstanding,
|
|
f_b_nreqs, f_b_nacks, f_b_outstanding,
|
|
f_nreqs, f_nacks, f_outstanding
|
|
`endif
|
|
);
|
parameter DW=32, AW=32;
|
parameter DW=32, AW=32;
|
parameter SCHEME="ALTERNATING";
|
parameter SCHEME="ALTERNATING";
|
parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0;
|
parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0;
|
`ifdef FORMAL
|
parameter F_MAX_STALL = 3;
|
|
parameter F_MAX_ACK_DELAY = 3;
|
parameter F_LGDEPTH=3;
|
parameter F_LGDEPTH=3;
|
`endif
|
|
|
|
//
|
//
|
input wire i_clk, i_reset;
|
input wire i_clk, i_reset;
|
// Bus A
|
// Bus A
|
input wire i_a_cyc, i_a_stb, i_a_we;
|
input wire i_a_cyc, i_a_stb, i_a_we;
|
| Line 78... |
Line 106... |
output wire o_cyc, o_stb, o_we;
|
output wire o_cyc, o_stb, o_we;
|
output wire [(AW-1):0] o_adr;
|
output wire [(AW-1):0] o_adr;
|
output wire [(DW-1):0] o_dat;
|
output wire [(DW-1):0] o_dat;
|
output wire [(DW/8-1):0] o_sel;
|
output wire [(DW/8-1):0] o_sel;
|
input wire i_ack, i_stall, i_err;
|
input wire i_ack, i_stall, i_err;
|
|
//
|
|
`ifdef FORMAL
|
|
output wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding,
|
|
f_a_nreqs, f_a_nacks, f_a_outstanding,
|
|
f_b_nreqs, f_b_nacks, f_b_outstanding;
|
|
`endif
|
|
|
// Go high immediately (new cycle) if ...
|
// Go high immediately (new cycle) if ...
|
// Previous cycle was low and *someone* is requesting a bus cycle
|
// Previous cycle was low and *someone* is requesting a bus cycle
|
// Go low immadiately if ...
|
// Go low immadiately if ...
|
// We were just high and the owner no longer wants the bus
|
// We were just high and the owner no longer wants the bus
|
| Line 200... |
Line 234... |
// verilator lint_on UNUSED
|
// verilator lint_on UNUSED
|
|
|
`ifdef FORMAL
|
`ifdef FORMAL
|
|
|
`ifdef WBARBITER
|
`ifdef WBARBITER
|
reg f_last_clk;
|
|
initial assume(!i_clk);
|
|
always @($global_clock)
|
|
begin
|
|
assume(i_clk != f_last_clk);
|
|
f_last_clk <= i_clk;
|
|
end
|
|
`define ASSUME assume
|
`define ASSUME assume
|
`else
|
`else
|
`define ASSUME assert
|
`define ASSUME assert
|
`endif
|
`endif
|
|
|
reg f_past_valid;
|
reg f_past_valid;
|
initial f_past_valid = 1'b0;
|
initial f_past_valid = 1'b0;
|
always @($global_clock)
|
always @(posedge i_clk)
|
f_past_valid <= 1'b1;
|
f_past_valid <= 1'b1;
|
|
|
initial `ASSUME(!i_a_cyc);
|
initial `ASSUME(!i_a_cyc);
|
initial `ASSUME(!i_a_stb);
|
initial `ASSUME(!i_a_stb);
|
|
|
| Line 226... |
Line 254... |
initial `ASSUME(!i_b_stb);
|
initial `ASSUME(!i_b_stb);
|
|
|
initial `ASSUME(!i_ack);
|
initial `ASSUME(!i_ack);
|
initial `ASSUME(!i_err);
|
initial `ASSUME(!i_err);
|
|
|
|
always @(*)
|
|
if (!f_past_valid)
|
|
`ASSUME(i_reset);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
if (o_cyc)
|
if (o_cyc)
|
assert((i_a_cyc)||(i_b_cyc));
|
assert((i_a_cyc)||(i_b_cyc));
|
if ((f_past_valid)&&($past(o_cyc))&&(o_cyc))
|
if ((f_past_valid)&&($past(o_cyc))&&(o_cyc))
|
assert($past(r_a_owner) == r_a_owner);
|
assert($past(r_a_owner) == r_a_owner);
|
end
|
end
|
|
|
wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding,
|
|
f_a_nreqs, f_a_nacks, f_a_outstanding,
|
|
f_b_nreqs, f_b_nacks, f_b_outstanding;
|
|
|
|
fwb_master #(.DW(DW), .AW(AW),
|
fwb_master #(.DW(DW), .AW(AW),
|
.F_MAX_STALL(0),
|
.F_MAX_STALL(F_MAX_STALL),
|
.F_LGDEPTH(F_LGDEPTH),
|
.F_LGDEPTH(F_LGDEPTH),
|
.F_MAX_ACK_DELAY(0),
|
.F_MAX_ACK_DELAY(F_MAX_ACK_DELAY),
|
.F_OPT_RMW_BUS_OPTION(1),
|
.F_OPT_RMW_BUS_OPTION(1),
|
.F_OPT_DISCONTINUOUS(1))
|
.F_OPT_DISCONTINUOUS(1))
|
f_wbm(i_clk, i_reset,
|
f_wbm(i_clk, i_reset,
|
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel,
|
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel,
|
i_ack, i_stall, 32'h0, i_err,
|
i_ack, i_stall, 32'h0, i_err,
|
| Line 296... |
Line 324... |
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if ((f_past_valid)&&(r_a_owner != $past(r_a_owner)))
|
if ((f_past_valid)&&(r_a_owner != $past(r_a_owner)))
|
assert(!$past(o_cyc));
|
assert(!$past(o_cyc));
|
|
|
|
reg f_prior_a_ack, f_prior_b_ack;
|
|
|
|
initial f_prior_a_ack = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((i_reset)||(o_a_err)||(o_b_err))
|
|
f_prior_a_ack = 1'b0;
|
|
else if ((o_cyc)&&(o_a_ack))
|
|
f_prior_a_ack <= 1'b1;
|
|
|
|
initial f_prior_b_ack = 1'b0;
|
|
always @(posedge i_clk)
|
|
if ((i_reset)||(o_a_err)||(o_b_err))
|
|
f_prior_b_ack = 1'b0;
|
|
else if ((o_cyc)&&(o_b_ack))
|
|
f_prior_b_ack <= 1'b1;
|
|
|
|
always @(posedge i_clk)
|
|
begin
|
|
cover(f_prior_b_ack && o_cyc && o_a_ack);
|
|
|
|
cover((o_cyc && o_a_ack)
|
|
&&($past(o_cyc && o_a_ack))
|
|
&&($past(o_cyc && o_a_ack,2)));
|
|
|
|
|
|
cover(f_prior_a_ack && o_cyc && o_b_ack);
|
|
|
|
cover((o_cyc && o_b_ack)
|
|
&&($past(o_cyc && o_b_ack))
|
|
&&($past(o_cyc && o_b_ack,2)));
|
|
end
|
|
|
|
always @(*)
|
|
cover(o_cyc && o_b_ack);
|
`endif
|
`endif
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
