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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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module wbm2axisp #(
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module wbm2axisp #(
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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// This is an int between 1-16
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// This is an int between 1-16
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter AW = 28, // Wishbone address width
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parameter AW = 28, // Wishbone address width
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parameter DW = 128 // Wishbone data width
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parameter DW = 32, // Wishbone data width
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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) (
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) (
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input i_clk, // System clock
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input i_clk, // System clock
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input i_reset,// Wishbone reset signal
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input i_reset,// Wishbone reset signal
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// AXI write address channel signals
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// AXI write address channel signals
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output reg o_axi_wvalid, // Write address valid
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output reg o_axi_wvalid, // Write address valid
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// AXI write data channel signals
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// AXI write data channel signals
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input i_axi_wd_wready, // Write data ready
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input i_axi_wd_wready, // Write data ready
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
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output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
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output reg [DW-1:0] o_axi_wd_data, // Write data
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output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data
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output reg [DW/8-1:0] o_axi_wd_strb, // Write strobes
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output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes
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output wire o_axi_wd_last, // Last write transaction
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output wire o_axi_wd_last, // Last write transaction
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output reg o_axi_wd_valid, // Write valid
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output reg o_axi_wd_valid, // Write valid
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|
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// AXI write response channel signals
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// AXI write response channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID
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input [C_AXI_ID_WIDTH-1:0] i_axi_wd_bid, // Response ID
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| Line 102... |
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// AXI read data channel signals
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// AXI read data channel signals
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input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
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input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
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input [1:0] i_axi_rd_rresp, // Read response
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input [1:0] i_axi_rd_rresp, // Read response
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input i_axi_rd_rvalid, // Read reponse valid
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input i_axi_rd_rvalid, // Read reponse valid
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input [DW-1:0] i_axi_rd_data, // Read data
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input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data
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input i_axi_rd_last, // Read last
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input i_axi_rd_last, // Read last
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output wire o_axi_rd_rready, // Read Response ready
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output wire o_axi_rd_rready, // Read Response ready
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|
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// We'll share the clock and the reset
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// We'll share the clock and the reset
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc,
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input [AW-1:0] i_wb_addr;
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input i_wb_stb,
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input [DW-1:0] i_wb_data;
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input i_wb_we,
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output reg o_wb_ack;
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input [AW-1:0] i_wb_addr,
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output wire o_wb_stall;
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input [DW-1:0] i_wb_data,
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output reg [DW-1:0] o_wb_data;
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input [3:0] i_wb_sel,
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output reg o_wb_err;
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output reg o_wb_ack,
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output wire o_wb_stall,
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output reg [DW-1:0] o_wb_data,
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output reg o_wb_err
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);
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);
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//*****************************************************************************
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//*****************************************************************************
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// Parameter declarations
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// Parameter declarations
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//*****************************************************************************
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//*****************************************************************************
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| Line 201... |
Line 205... |
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// Write data logic
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// Write data logic
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assign o_axi_wd_wid = transaction_id;
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assign o_axi_wd_wid = transaction_id;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wbdata };
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o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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case(i_wb_addr[1:0])
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case(i_wb_addr[1:0])
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2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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| Line 228... |
Line 232... |
// Reorder FIFO
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// Reorder FIFO
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//
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//
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localparam LGFIFOLN = C_AXI_ID_WIDTH;
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localparam LGFIFOLN = C_AXI_ID_WIDTH;
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localparam FIFOLN = (1<<LGFIFOLN);
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localparam FIFOLN = (1<<LGFIFOLN);
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// FIFO reorder buffer
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// FIFO reorder buffer
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reg [(DW-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg reorder_fifo_valid[0:(FIFOLN-1)];
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg reorder_fifo_err [0:(FIFOLN-1)];
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] low_addr;
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always @(posedge i_clk)
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if ((i_wb_stb)&&(!o_wb_stall))
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low_addr <= i_wb_addr[1:0];
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always @(posedge i_clk)
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if ((o_axi_rvalid)&&(i_axi_rready))
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reorder_fifo_addr[o_axi_rid] <= low_addr;
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wire [(LGFIFOLN-1):0] fifo_head;
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assign fifo_head = transaction_id;
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assign fifo_head = transaction_id;
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// Let's do some math to figure out where the FIFO head will
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// Let's do some math to figure out where the FIFO head will
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// point to next, but let's also insist that it be LGFIFOLN
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// point to next, but let's also insist that it be LGFIFOLN
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// bits in size as well. This'll be part of the fifo_full
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// bits in size as well. This'll be part of the fifo_full
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
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reorder_fifo_data[i_axi_rd_bid]<= i_axi_rd_data;
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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begin
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begin
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reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
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reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
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reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_resp[1];
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reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];
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end
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end
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if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
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if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
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begin
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begin
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reorder_fifo_valid[i_axi_wd_bid] = 1'b1;
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reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
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reorder_fifo_err[i_axi_wd_bid] = i_axi_wd_bresp[1];
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reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
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end
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end
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o_wb_data <= reorder_fifo_data[fifo_tail];
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case(reorder_fifo_addr[1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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if (reorder_fifo_valid[fifo_tail])
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if (reorder_fifo_valid[fifo_tail])
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begin
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begin
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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o_wb_err <= reorder_fifo_err[fifo_tail];
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o_wb_err <= reorder_fifo_err[fifo_tail];
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fifo_tail <= fifo_tail + 6'h1;
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fifo_tail <= fifo_tail + 6'h1;
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Line 302... |
o_wb_err <= 1'b0;
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o_wb_err <= 1'b0;
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o_wb_ack <= 1'b0;
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o_wb_ack <= 1'b0;
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end
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end
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end
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end
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reg r_fifo_full;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (!i_wb_cyc)
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if (!i_wb_cyc)
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r_fifo_full <= 1'b0;
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r_fifo_full <= 1'b0;
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else if ((i_wb_stb)&&(~o_wb_stall)
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else if ((i_wb_stb)&&(~o_wb_stall)
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| Line 294... |
Line 319... |
else
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else
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r_fifo_full <= (fifo_tail==n_fifo_head);
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r_fifo_full <= (fifo_tail==n_fifo_head);
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end
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end
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assign w_fifo_full = r_fifo_full;
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assign w_fifo_full = r_fifo_full;
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end else begin
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end else begin
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w_fifo_full = 1'b0;
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assign w_fifo_full = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_data <= i_axi_rd_data;
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o_wb_data <= i_axi_rd_data;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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o_wb_ack <= ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
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||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
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||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
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o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
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||((i_axi_rd_rvalid)&&(i_axi_rd_resp[1]))
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||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))
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||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
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||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
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end
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end endgenerate
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// Now, the difficult signal ... the stall signal
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// Now, the difficult signal ... the stall signal
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// Let's build for a single cycle input ... and only stall if something
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// Let's build for a single cycle input ... and only stall if something
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// outgoing is valid and nothing is ready.
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// outgoing is valid and nothing is ready.
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assign o_wb_stall = (i_wb_cyc)&&(
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assign o_wb_stall = (i_wb_cyc)&&(
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(w_fifo_full)
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(w_fifo_full)
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||((o_axi_wvalid)&&(!i_axi_wready))
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||((o_axi_wvalid)&&(!i_axi_wready))
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||((o_axi_wd_valid)&&(!i_axi_wd_bready))
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||((o_axi_wd_valid)&&(!i_axi_wd_wready))
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||((o_axi_rvalid)&&(!i_axi_rready)));
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||((o_axi_rvalid)&&(!i_axi_rready)));
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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