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Line 55... |
module wbm2axisp #(
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module wbm2axisp #(
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
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// This is an int between 1-16
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// This is an int between 1-16
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
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parameter AW = 28, // Wishbone address width
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parameter AW = 28, // Wishbone address width
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parameter DW = 32, // Wishbone data width
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parameter DW = 128, // Wishbone data width
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
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) (
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) (
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input i_clk, // System clock
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input i_clk, // System clock
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input i_reset,// Wishbone reset signal
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input i_reset,// Wishbone reset signal
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Line 113... |
input i_wb_cyc,
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input i_wb_cyc,
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input i_wb_stb,
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input i_wb_stb,
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input i_wb_we,
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input i_wb_we,
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input [AW-1:0] i_wb_addr,
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input [AW-1:0] i_wb_addr,
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input [DW-1:0] i_wb_data,
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input [DW-1:0] i_wb_data,
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input [3:0] i_wb_sel,
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input [(DW/8-1):0] i_wb_sel,
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output reg o_wb_ack,
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output reg o_wb_ack,
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output wire o_wb_stall,
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output wire o_wb_stall,
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output reg [DW-1:0] o_wb_data,
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output reg [DW-1:0] o_wb_data,
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output reg o_wb_err
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output reg o_wb_err
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);
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);
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||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
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||(o_wb_stall)&&(o_axi_rvalid)&&(!i_axi_rready);
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// Write data logic
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// Write data logic
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assign o_axi_wd_wid = transaction_id;
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assign o_axi_wd_wid = transaction_id;
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generate
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if (DW == 32)
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begin
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (!o_wb_stall)
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if (!o_wb_stall)
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Line 218... |
2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
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2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
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2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
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2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
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2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
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endcase
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endcase
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_axi_wd_data <= i_wb_data;
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_axi_wd_strb <= i_wb_sel;
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end endgenerate
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assign o_axi_wd_last = 1'b1;
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assign o_axi_wd_last = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
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o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
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||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
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||(o_wb_stall)&&(o_axi_wd_valid)&&(!i_axi_wd_wready);
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// FIFO reorder buffer
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// FIFO reorder buffer
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(LGFIFOLN-1):0] fifo_tail;
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_valid;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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reg [(FIFOLN-1):0] reorder_fifo_err;
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if (DW == 32)
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begin
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
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reg [1:0] low_addr;
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reg [1:0] low_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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Line 264... |
low_addr <= i_wb_addr[1:0];
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low_addr <= i_wb_addr[1:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((o_axi_rvalid)&&(i_axi_rready))
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if ((o_axi_rvalid)&&(i_axi_rready))
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reorder_fifo_addr[o_axi_rid] <= low_addr;
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reorder_fifo_addr[o_axi_rid] <= low_addr;
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always @(posedge i_clk)
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case(reorder_fifo_addr[1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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end else if (DW == 128)
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begin
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always @(posedge i_clk)
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o_wb_data <= reorder_fifo_data[fifo_tail];
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end
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wire [(LGFIFOLN-1):0] fifo_head;
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wire [(LGFIFOLN-1):0] fifo_head;
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assign fifo_head = transaction_id;
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assign fifo_head = transaction_id;
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// Let's do some math to figure out where the FIFO head will
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// Let's do some math to figure out where the FIFO head will
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begin
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begin
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reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
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reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
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reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
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reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
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end
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end
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case(reorder_fifo_addr[1:0])
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2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
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2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
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2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
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2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
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endcase
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if (reorder_fifo_valid[fifo_tail])
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if (reorder_fifo_valid[fifo_tail])
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begin
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begin
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o_wb_ack <= 1'b1;
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o_wb_ack <= 1'b1;
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o_wb_err <= reorder_fifo_err[fifo_tail];
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o_wb_err <= reorder_fifo_err[fifo_tail];
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fifo_tail <= fifo_tail + 6'h1;
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fifo_tail <= fifo_tail + 6'h1;
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