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[/] [wb4pb/] [trunk/] [impl/] [avnet_sp3a_eval_gpio_vhd.vhd] - Diff between revs 24 and 28
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| Rev 24 |
Rev 28 |
| Line 166... |
Line 166... |
begin
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begin
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-- reset synchronisation
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-- reset synchronisation
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process(clk)
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process(clk)
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begin
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begin
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if rising_edge(clk) then
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rst <= FPGA_RESET;
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rst <= FPGA_RESET;
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end if;
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end process;
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end process;
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clk <= CLK_16MHZ;
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clk <= CLK_16MHZ;
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-- module instances
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-- module instances
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-------------------
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-------------------
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