URL
https://opencores.org/ocsvn/wb_size_bridge/wb_size_bridge/trunk
Show entire file |
Details |
Blame |
View Log
Rev 6 |
Rev 7 |
Line 93... |
Line 93... |
|
|
end
|
end
|
|
|
32: begin
|
32: begin
|
initial
|
initial
|
begin
|
|
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
|
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
|
$display( "###- wb_slave_model(): Not yet supported " );
|
|
$stop();
|
always @ (posedge clk_i)
|
end
|
if (we_i & cyc_i & stb_i & sel_i[0])
|
|
ram[{adr_i[AWIDTH-1:2], 2'b00}] <= dat_i[7:0];
|
|
|
|
always @ (posedge clk_i)
|
|
if (we_i & cyc_i & stb_i & sel_i[1])
|
|
ram[{adr_i[AWIDTH-1:2], 2'b01}] <= dat_i[15:8];
|
|
|
|
always @ (posedge clk_i)
|
|
if (we_i & cyc_i & stb_i & sel_i[2])
|
|
ram[{adr_i[AWIDTH-1:2], 2'b10}] <= dat_i[23:16];
|
|
|
|
always @ (posedge clk_i)
|
|
if (we_i & cyc_i & stb_i & sel_i[3])
|
|
ram[{adr_i[AWIDTH-1:2], 2'b11}] <= dat_i[31:24];
|
|
|
|
assign dat_o = { ram[{adr_i[AWIDTH-1:2], 2'b11}], ram[{adr_i[AWIDTH-1:2], 2'b10}], ram[{adr_i[AWIDTH-1:2], 2'b01}], ram[{adr_i[AWIDTH-1:2], 2'b00}] };
|
|
|
end
|
end
|
|
|
default: begin
|
default: begin
|
localparam SLAVE_SIZE = -1;
|
localparam SLAVE_SIZE = -1;
|
initial
|
initial
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.