Line 48... |
Line 48... |
#include "ddrsdramsim.h"
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#include "ddrsdramsim.h"
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void BANKINFO::tick(int cmd, unsigned addr) {
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void BANKINFO::tick(int cmd, unsigned addr) {
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switch(cmd) {
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switch(cmd) {
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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m_state = 6;
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m_state = 6;
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// While the specification allows precharging an already
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// precharged bank, we can keep that from happening
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// here:
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// assert(m_state&7);
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// Only problem is, this will currently break our
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// refresh logic.
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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m_state = 1;
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m_state = 1;
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m_row = addr & 0x7fff;
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m_row = addr & 0x7fff;
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break;
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break;
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Line 215... |
Line 221... |
} else {
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} else {
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// In operational mode!!
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// In operational mode!!
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m_clocks_since_refresh++;
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m_clocks_since_refresh++;
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assert(m_clocks_since_refresh < (int)ckREFIn);
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assert(m_clocks_since_refresh < (int)ckREFIn);
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printf("Clocks to refresh should be %4d-%4d = %4d = 0x%04x\n",
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ckREFIn, m_clocks_since_refresh,
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ckREFIn- m_clocks_since_refresh,
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ckREFIn- m_clocks_since_refresh);
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switch(cmd) {
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switch(cmd) {
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case DDR_MRSET:
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case DDR_MRSET:
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assert(0&&"Modes should only be set in reset startup");
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assert(0&&"Modes should only be set in reset startup");
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_MRSET,0);
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m_bank[i].tick(DDR_MRSET,0);
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Line 258... |
Line 260... |
assert((addr&7)==0);
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assert((addr&7)==0);
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m_bank[ba].tick(DDR_WRITE, addr);
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m_bank[ba].tick(DDR_WRITE, addr);
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
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if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
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unsigned caddr = m_bank[ba].m_row;
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unsigned caddr = m_bank[ba].m_row;
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caddr <<= 13;
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caddr <<= 3;
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caddr |= ba;
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caddr |= ba;
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caddr <<= 10;
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caddr <<= 10;
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caddr |= addr;
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caddr |= addr;
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caddr &= ~7;
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caddr &= ~7;
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caddr >>= 1;
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caddr >>= 1;
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Line 300... |
Line 302... |
assert((addr&7)==0);
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assert((addr&7)==0);
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m_bank[ba].tick(DDR_READ, addr);
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m_bank[ba].tick(DDR_READ, addr);
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
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if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
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unsigned caddr = m_bank[ba].m_row;
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unsigned caddr = m_bank[ba].m_row;
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caddr <<= 13;
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caddr <<= 3;
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caddr |= ba;
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caddr |= ba;
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caddr <<= 10;
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caddr <<= 10;
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caddr |= addr;
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caddr |= addr;
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caddr &= ~7;
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caddr &= ~7;
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caddr >>= 1;
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caddr >>= 1;
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BUSTIMESLOT *tp;
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BUSTIMESLOT *tp;
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tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
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int offset = (m_busloc+ckCL+1)&(NTIMESLOTS-1);
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tp = &m_bus[(offset)&(NTIMESLOTS-1)];
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tp->m_data = m_mem[caddr];
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tp->m_data = m_mem[caddr];
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tp->m_addr = caddr;
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tp->m_addr = caddr;
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tp->m_used = 1;
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tp->m_used = 1;
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tp->m_read = 1;
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tp->m_read = 1;
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tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
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tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
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tp->m_data = m_mem[caddr+1];
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tp->m_data = m_mem[caddr+1];
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tp->m_addr = caddr+1;
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tp->m_addr = caddr+1;
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tp->m_used = 1;
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tp->m_used = 1;
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tp->m_read = 1;
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tp->m_read = 1;
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tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
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tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
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tp->m_data = m_mem[caddr+2];
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tp->m_data = m_mem[caddr+2];
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tp->m_addr = caddr+2;
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tp->m_addr = caddr+2;
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tp->m_used = 1;
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tp->m_used = 1;
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tp->m_read = 1;
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tp->m_read = 1;
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tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
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tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
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tp->m_data = m_mem[caddr+3];
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tp->m_data = m_mem[caddr+3];
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tp->m_addr = caddr+3;
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tp->m_addr = caddr+3;
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tp->m_used = 1;
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tp->m_used = 1;
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tp->m_read = 1;
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tp->m_read = 1;
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} break;
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} break;
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