| Line 42... |
Line 42... |
`define DDR_REFRESH 4'b0001
|
`define DDR_REFRESH 4'b0001
|
`define DDR_PRECHARGE 4'b0010
|
`define DDR_PRECHARGE 4'b0010
|
`define DDR_ACTIVATE 4'b0011
|
`define DDR_ACTIVATE 4'b0011
|
`define DDR_WRITE 4'b0100
|
`define DDR_WRITE 4'b0100
|
`define DDR_READ 4'b0101
|
`define DDR_READ 4'b0101
|
|
`define DDR_ZQS 4'b0110
|
`define DDR_NOOP 4'b0111
|
`define DDR_NOOP 4'b0111
|
//`define DDR_DESELECT 4'b1???
|
//`define DDR_DESELECT 4'b1???
|
//
|
//
|
// In this controller, 24-bit commands tend to be passed around. These
|
// In this controller, 24-bit commands tend to be passed around. These
|
// 'commands' are bit fields. Here we specify the bits associated with
|
// 'commands' are bit fields. Here we specify the bits associated with
|
| Line 66... |
Line 67... |
module wbddrsdram(i_clk, i_reset,
|
module wbddrsdram(i_clk, i_reset,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_ddr_reset_n, o_ddr_cke,
|
o_ddr_reset_n, o_ddr_cke,
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
|
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_dir,
|
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
|
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
|
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
|
|
o_cmd_accepted);
|
parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
|
parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
|
CKRFC = 140;
|
CKRFC = 140,
|
|
CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
|
input i_clk, i_reset;
|
input i_clk, i_reset;
|
// Wishbone inputs
|
// Wishbone inputs
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input i_wb_cyc, i_wb_stb, i_wb_we;
|
input [25:0] i_wb_addr;
|
input [25:0] i_wb_addr;
|
input [31:0] i_wb_data;
|
input [31:0] i_wb_data;
|
| Line 85... |
Line 88... |
output wire o_ddr_reset_n, o_ddr_cke;
|
output wire o_ddr_reset_n, o_ddr_cke;
|
// Control outputs
|
// Control outputs
|
output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
|
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
|
// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
|
output wire o_ddr_dqs;
|
output wire o_ddr_dqs;
|
output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_dir;
|
output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
|
// Address outputs
|
// Address outputs
|
output reg [13:0] o_ddr_addr;
|
output reg [13:0] o_ddr_addr;
|
output reg [2:0] o_ddr_ba;
|
output reg [2:0] o_ddr_ba;
|
// And the data inputs and outputs
|
// And the data inputs and outputs
|
output reg [31:0] o_ddr_data;
|
output reg [31:0] o_ddr_data;
|
input i_ddr_data;
|
input i_ddr_data;
|
|
// And just for the test bench
|
|
output reg o_cmd_accepted;
|
|
|
|
always @(posedge i_clk)
|
|
o_cmd_accepted <= (i_wb_stb)&&(~o_wb_stall);
|
|
|
reg drive_dqs;
|
reg drive_dqs;
|
|
|
// The pending transaction
|
// The pending transaction
|
reg [31:0] r_data;
|
reg [31:0] r_data;
|
| Line 172... |
Line 180... |
reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
|
reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
|
end else if (!reset_ztimer)
|
end else if (!reset_ztimer)
|
;
|
;
|
else if (reset_instruction[`DDR_RSTDONE])
|
else if (reset_instruction[`DDR_RSTDONE])
|
reset_override <= 1'b0;
|
reset_override <= 1'b0;
|
else if (reset_instruction[`DDR_RSTTIMER])
|
else
|
begin
|
|
if (reset_instruction[`DDR_NOPTIMER])
|
|
reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
|
|
end else begin
|
|
reset_cmd <= reset_instruction[22:0];
|
reset_cmd <= reset_instruction[22:0];
|
end
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_reset)
|
if (i_reset)
|
o_ddr_cke <= 1'b0;
|
o_ddr_cke <= 1'b0;
|
else if ((reset_override)&&(reset_ztimer))
|
else if ((reset_override)&&(reset_ztimer))
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
|
|
initial reset_ztimer = 1'b1; // Is the timer zero?
|
initial reset_ztimer = 1'b0; // Is the timer zero?
|
initial reset_timer = 17'h00;
|
initial reset_timer = 17'h01;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_reset)
|
if (i_reset)
|
begin
|
begin
|
reset_ztimer <= 1'b0;
|
reset_ztimer <= 1'b0;
|
reset_timer <= 17'h00;
|
reset_timer <= 17'd1;
|
end else if (!reset_ztimer)
|
end else if (!reset_ztimer)
|
begin
|
begin
|
reset_ztimer <= (reset_timer == 17'h01);
|
reset_ztimer <= (reset_timer == 17'h01);
|
reset_timer <= reset_timer - 17'h01;
|
reset_timer <= reset_timer - 17'h01;
|
end else if (reset_instruction[`DDR_RSTTIMER])
|
end else if (reset_instruction[`DDR_RSTTIMER])
|
begin
|
begin
|
reset_ztimer <= 1'b0;
|
reset_ztimer <= 1'b0;
|
reset_timer <= reset_instruction[16:0];
|
reset_timer <= reset_instruction[16:0];
|
end
|
end
|
|
|
|
wire [18:0] w_ckXPR = CKXPR, w_ckRST = 4, w_ckRP = 3,
|
|
w_ckRFC = CKRFC;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(reset_address) // RSTDONE, TIMER, CKE, ??
|
if (i_reset)
|
|
reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
|
|
else case(reset_address) // RSTDONE, TIMER, CKE, ??
|
|
// 1. Reset asserted (active low) for 200 us. (@200MHz)
|
4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
|
4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
|
|
// 2. Reset de-asserted, wait 500 us before asserting CKE
|
4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
|
4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
|
4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
|
// 3. Assert CKE, wait minimum of Reset CKE Exit time
|
4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
|
4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckXPR };
|
4'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
|
// 4. Look MR2. (1CK, no TIMER)
|
4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
|
4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2,
|
4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
|
5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
|
4'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
|
// 3. Wait 4 clocks (tMRD)
|
|
4'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 19'h04 };
|
|
// 5. Set MR1
|
|
4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1,
|
|
3'h0, // Reserved for Future Use (RFU)
|
|
1'b0, // Qoff - output buffer enabled
|
|
1'b1, // TDQS ... enabled
|
|
1'b0, // RFU
|
|
1'b0, // High order bit, Rtt_Nom (3'b011)
|
|
1'b0, // RFU
|
|
//
|
|
1'b0, // Disable write-leveling
|
|
1'b1, // Mid order bit of Rtt_Nom
|
|
1'b0, // High order bit of Output Drvr Impedence Ctrl
|
|
2'b0, // Additive latency = 0
|
|
1'b1, // Low order bit of Rtt_Nom
|
|
1'b1, // DIC set to 2'b01
|
|
1'b1 }; // MRS1, DLL enable
|
|
// 7. Wait another 4 clocks
|
|
4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 19'h04 };
|
|
// 8. Send MRS0
|
|
4'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0,
|
|
3'b0, // Reserved for future use
|
|
1'b0, // PPD control, (slow exit(DLL off))
|
|
3'b1, // Write recovery for auto precharge
|
|
1'b0, // DLL Reset (No)
|
|
//
|
|
1'b0, // TM mode normal
|
|
3'b01, // High 3-bits, CAS latency (=4'b0010 = 4'd5)
|
|
1'b0, // Read burst type = nibble sequential
|
|
1'b0, // Low bit of cas latency
|
|
2'b0 }; // Burst length = 8 (Fixed)
|
|
// 9. Wait tMOD, is max(12 clocks, 15ns)
|
|
4'h8: reset_instruction <= { 4'h7, `DDR_NOOP, 19'h0c };
|
|
// 10. Issue a ZQCL command to start ZQ calibration, A10 is high
|
|
4'h9: reset_instruction <= { 4'h7, `DDR_ZQS, 8'h0, 1'b1, 10'h0};
|
|
//11.Wait for both tDLLK and tZQinit completed, both are 512 cks
|
|
4'ha: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd512 };
|
|
// 12. Precharge all command
|
|
4'hb: reset_instruction <= { 4'h7, `DDR_PRECHARGE, 8'h0, 1'b1, 10'h0 };
|
|
// 13. Wait for the precharge to complete
|
|
4'hc: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRP };
|
|
// 14. A single Auto Refresh commands
|
|
4'hd: reset_instruction <= { 4'h7, `DDR_REFRESH, 19'h00 };
|
|
// 15. Wait for the auto refresh to complete
|
|
4'he: reset_instruction <= { 4'h7, `DDR_NOOP, w_ckRFC };
|
|
// Two Auto Refresh commands
|
default:
|
default:
|
reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
|
reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
|
endcase
|
endcase
|
// reset_instruction <= reset_mem[reset_address];
|
// reset_instruction <= reset_mem[reset_address];
|
|
|
|
initial reset_address = 4'h0;
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (i_reset)
|
if (i_reset)
|
reset_address <= 4'h0;
|
reset_address <= 4'h0;
|
else if (reset_ztimer)
|
else if (reset_ztimer)
|
reset_address <= reset_address + 4'h1;
|
reset_address <= reset_address + 4'h1;
|
| Line 386... |
Line 441... |
bus_subaddr[4] <= bus_subaddr[3];
|
bus_subaddr[4] <= bus_subaddr[3];
|
bus_subaddr[3] <= bus_subaddr[2];
|
bus_subaddr[3] <= bus_subaddr[2];
|
bus_subaddr[2] <= bus_subaddr[1];
|
bus_subaddr[2] <= bus_subaddr[1];
|
bus_subaddr[1] <= bus_subaddr[0];
|
bus_subaddr[1] <= bus_subaddr[0];
|
bus_subaddr[0] <= 2'h3;
|
bus_subaddr[0] <= 2'h3;
|
if (cmd[22:19] == `DDR_READ)
|
if ((!reset_override)&&(!need_refresh)&&(!need_close_bank)
|
|
&&(!need_open_bank)&&(valid_bank))
|
begin
|
begin
|
bus_active[3:0]<= 4'hf; // Once per clock
|
bus_active[3:0]<= 4'hf; // Once per clock
|
bus_read[3:0] <= 4'hf; // These will be reads
|
bus_read[3:0] <= 4'hf; // These will be reads
|
bus_subaddr[3] <= 2'h0;
|
bus_subaddr[3] <= 2'h0;
|
bus_subaddr[2] <= 2'h1;
|
bus_subaddr[2] <= 2'h1;
|
bus_subaddr[1] <= 2'h2;
|
bus_subaddr[1] <= 2'h2;
|
end else if (cmd == `DDR_WRITE)
|
|
begin
|
bus_read[3:0] <= (r_we)? 4'h0:4'hf;
|
bus_active[3:0] <= 4'hf;
|
|
// bus_read[7:4] = 4'h0;
|
|
bus_subaddr[3] <= 2'h0;
|
|
bus_subaddr[2] <= 2'h1;
|
|
bus_subaddr[1] <= 2'h2;
|
|
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
drive_dqs <= (~bus_read[8])&&(|bus_active[8:7]);
|
drive_dqs <= (~bus_read[8])&&(|bus_active[8:7]);
|
| Line 430... |
Line 481... |
r_we <= i_wb_we;
|
r_we <= i_wb_we;
|
r_addr <= i_wb_addr;
|
r_addr <= i_wb_addr;
|
r_data <= i_wb_data;
|
r_data <= i_wb_data;
|
r_row <= i_wb_addr[25:11];
|
r_row <= i_wb_addr[25:11];
|
r_bank <= i_wb_addr[10:8];
|
r_bank <= i_wb_addr[10:8];
|
r_col <= { i_wb_addr[7:2], 2'b00 }; // 9:2
|
r_col <= { i_wb_addr[7:0], 2'b00 }; // 9:2
|
r_sub <= i_wb_addr[1:0];
|
r_sub <= i_wb_addr[1:0];
|
|
|
// pre-emptive work
|
// pre-emptive work
|
r_nxt_row <= i_wb_addr[25:11]+15'h1;
|
r_nxt_row <= i_wb_addr[25:11]+15'h1;
|
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
|
r_nxt_bank <= i_wb_addr[10:8]+3'h1;
|
| Line 462... |
Line 513... |
&&(r_nxt_row != bank_address[r_nxt_bank])
|
&&(r_nxt_row != bank_address[r_nxt_bank])
|
&&(!need_close_this_bank);
|
&&(!need_close_this_bank);
|
|
|
close_bank_cmd <= (maybe_close_next_bank)
|
close_bank_cmd <= (maybe_close_next_bank)
|
? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[14:10], 1'b0, r_nxt_row[9:0] }
|
? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[14:10], 1'b0, r_nxt_row[9:0] }
|
: { `DDR_PRECHARGE, r_bank, r_row[15:11], 1'b0, r_row[9:0] };
|
: { `DDR_PRECHARGE, r_bank, r_row[14:10], 1'b0, r_row[9:0] };
|
|
|
|
|
need_open_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b00)
|
need_open_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b00)
|
&&(!last_open_bank);
|
&&(!last_open_bank);
|
last_open_bank <= need_open_bank;
|
last_open_bank <= need_open_bank;
|
| Line 521... |
Line 572... |
//
|
//
|
//
|
//
|
// Okay, let's look at the last assignment in our chain. It should look
|
// Okay, let's look at the last assignment in our chain. It should look
|
// something like:
|
// something like:
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_ddr_reset_n <= (~reset_override)||(reset_instruction[`DDR_RSTBIT]);
|
if (i_reset)
|
|
o_ddr_reset_n <= 1'b0;
|
|
else if (reset_ztimer)
|
|
o_ddr_reset_n <= reset_instruction[`DDR_RSTBIT];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
o_ddr_cke <= (~reset_override)||(reset_instruction[`DDR_CKEBIT]);
|
if (i_reset)
|
|
o_ddr_cke <= 1'b0;
|
|
else if (reset_ztimer)
|
|
o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
r_move <= 1'b0;
|
r_move <= 1'b0;
|
if (reset_override)
|
if (reset_override)
|
cmd <= reset_cmd[`DDR_CSBIT:0];
|
cmd <= reset_cmd[`DDR_CSBIT:0];
|
| Line 541... |
Line 598... |
else if ((valid_bank)&&(bus_active[2:0]==3'h0))
|
else if ((valid_bank)&&(bus_active[2:0]==3'h0))
|
begin
|
begin
|
cmd <= rw_cmd;
|
cmd <= rw_cmd;
|
r_move <= 1'b1;
|
r_move <= 1'b1;
|
end else
|
end else
|
cmd <= { `DDR_NOOP, rw_cmd[20:0] };
|
cmd <= { `DDR_NOOP, rw_cmd[(`DDR_WEBIT-1):0] };
|
end
|
end
|
|
|
reg [31:0] bus_data[8:0];
|
reg [31:0] bus_data[8:0];
|
|
|
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
|
assign o_ddr_cs_n = cmd[`DDR_CSBIT];
|
| Line 559... |
Line 616... |
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
assign w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
|
&&(o_ddr_addr[10]); // 5 bits
|
&&(o_ddr_addr[10]); // 5 bits
|
|
|
// Need to set o_wb_dqs high one clock prior to any read.
|
// Need to set o_wb_dqs high one clock prior to any read.
|
// As per spec, ODT = 0 during reads
|
// As per spec, ODT = 0 during reads
|
assign o_ddr_bus_dir = bus_read[8];
|
assign o_ddr_bus_oe = ~bus_read[8];
|
assign o_ddr_odt = o_ddr_bus_dir;
|
|
|
// ODT must be in high impedence while reset_n=0, then it can be set
|
|
// to low or high.
|
|
assign o_ddr_odt = o_ddr_bus_oe;
|
|
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
