| Line 378... |
Line 378... |
bank_status[7][0] <= 1'b0;
|
bank_status[7][0] <= 1'b0;
|
banks_are_closing <= 1'b1;
|
banks_are_closing <= 1'b1;
|
end else if (need_close_bank)
|
end else if (need_close_bank)
|
begin
|
begin
|
bank_status[close_bank_cmd[16:14]]
|
bank_status[close_bank_cmd[16:14]]
|
<= { bank_status[close_bank_cmd[16:14]][2:0], 1'b1 };
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<= { bank_status[close_bank_cmd[16:14]][2:0], 1'b0 };
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// bank_status[close_bank_cmd[16:14]][0] <= 1'b0;
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// bank_status[close_bank_cmd[16:14]][0] <= 1'b0;
|
end else if (need_open_bank)
|
end else if (need_open_bank)
|
begin
|
begin
|
bank_status[activate_bank_cmd[16:14]]
|
bank_status[activate_bank_cmd[16:14]]
|
<= { bank_status[activate_bank_cmd[16:14]][2:0], 1'b1 };
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<= { bank_status[activate_bank_cmd[16:14]][2:0], 1'b1 };
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| Line 392... |
Line 392... |
end else if ((valid_bank)&&(!r_move))
|
end else if ((valid_bank)&&(!r_move))
|
;
|
;
|
else if (maybe_close_next_bank)
|
else if (maybe_close_next_bank)
|
begin
|
begin
|
bank_status[maybe_close_cmd[16:14]]
|
bank_status[maybe_close_cmd[16:14]]
|
<= { bank_status[maybe_close_cmd[16:14]][2:0], 1'b1 };
|
<= { bank_status[maybe_close_cmd[16:14]][2:0], 1'b0 };
|
end else if (maybe_open_next_bank)
|
end else if (maybe_open_next_bank)
|
begin
|
begin
|
bank_status[maybe_open_cmd[16:14]]
|
bank_status[maybe_open_cmd[16:14]]
|
<= { bank_status[maybe_open_cmd[16:14]][2:0], 1'b1 };
|
<= { bank_status[maybe_open_cmd[16:14]][2:0], 1'b1 };
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
// bank_status[activate_bank_cmd[16:14]][0] <= 1'b1;
|
| Line 405... |
Line 405... |
end
|
end
|
end
|
end
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
// if (cmd[22:19] == `DDR_ACTIVATE)
|
// if (cmd[22:19] == `DDR_ACTIVATE)
|
if (need_open_bank)
|
if (w_this_opening_bank)
|
bank_address[activate_bank_cmd[16:14]]
|
bank_address[activate_bank_cmd[16:14]]
|
<= activate_bank_cmd[13:0];
|
<= activate_bank_cmd[13:0];
|
|
else if (!w_this_maybe_open)
|
|
bank_address[maybe_open_cmd[16:14]]
|
|
<= maybe_open_cmd[13:0];
|
|
|
//
|
//
|
//
|
//
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
// Okay, let's investigate when we need to do a refresh. Our plan will be to
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
// do 4 refreshes every tREFI*4 seconds. tREFI = 7.8us, but its a parameter
|
| Line 455... |
Line 458... |
end
|
end
|
|
|
wire [16:0] w_ckREFIn, w_ckREFRst;
|
wire [16:0] w_ckREFIn, w_ckREFRst;
|
assign w_ckREFIn[ 12: 0] = CKREFI4-5*CKRFC-2-10;
|
assign w_ckREFIn[ 12: 0] = CKREFI4-5*CKRFC-2-10;
|
assign w_ckREFIn[ 16:13] = 4'h0;
|
assign w_ckREFIn[ 16:13] = 4'h0;
|
assign w_ckREFRst[12: 0] = CKRFC-2-6;
|
assign w_ckREFRst[12: 0] = CKRFC-2-12;
|
assign w_ckREFRst[16:13] = 4'h0;
|
assign w_ckREFRst[16:13] = 4'h0;
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
if (reset_override)
|
if (reset_override)
|
refresh_instruction <= { 3'h0, `DDR_NOOP, w_ckREFIn };
|
refresh_instruction <= { 3'h0, `DDR_NOOP, w_ckREFIn };
|
| Line 488... |
Line 491... |
4'h7: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'h7: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'h8: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
4'h8: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
4'h9: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'h9: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'ha: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
4'ha: refresh_instruction <= { 3'h4, `DDR_REFRESH, 17'h00 };
|
4'hb: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'hb: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'hc: refresh_instruction <= { 3'h6, `DDR_NOOP, w_ckRFC };
|
4'hc: refresh_instruction <= { 3'h2, `DDR_NOOP, w_ckREFRst };
|
default:
|
default:
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
refresh_instruction <= { 3'h1, `DDR_NOOP, 17'h00 };
|
endcase
|
endcase
|
|
|
|
|
