| Line 60... |
Line 60... |
// = 123 * sample ~= 128 * sample = sample << 7.
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// = 123 * sample ~= 128 * sample = sample << 7.
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//
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//
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// Thus, by shifting our input sample value a touch, we can multiply by
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// Thus, by shifting our input sample value a touch, we can multiply by
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// nearly the exact constant we want.
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// nearly the exact constant we want.
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//
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//
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// OSERDES:
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// Okay, the first version was fun and worked ... okay, but ... can we do
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// better? I mean, we lost over 10dB by undersampling, and most(many?)
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// FPGA's have OSERDES components that will allow bits to toggle faster
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// than the FPGA clock rate. In other words, if we have an 80MHz clock,
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// we should be able to output samples at 320MHz, no?
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//
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// Let's do even one better than that: suppose we create outputs for a
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// 2-bit DAC. Of course, our chip doesn't have a 2-bit DAC, much less a
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// DAC at all, but could we create one from our I/O pins? For example,
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// if two I/O pins both produced a 1, the resulting field would be
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// stronger, right? What if they both produced a zero, same thing, right?
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// Now, what if one produced a 1 and one produced a 0? Would the fields
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// interfere with each other? You know, would they produce a sum field
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// that was better than just the one-bit produced field? Perhaps, with
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// only a 1-bit output, we get +/- 3. With a two bit output, we should
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// be able to get { -3, 0, 3 }, right? (Ignore scaling ...)
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//
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// A better two-bit output would probably be something like
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// { -3, -1, 1, 3 }. How can we produce something like that? Without a
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// proper ADC? Can we connect a majority of the pins to the high order
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// bit output, and some fewer number to the low order bit output?
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// Would this create a better field?
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//
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// The component created with `define OSERDES is designed to allow such
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// hypotheses to be tested.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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| Line 102... |
Line 129... |
input i_wb_addr;
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input i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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`ifdef USE_OSERDES
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output wire [7:0] o_tx;
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`else
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output wire o_tx;
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output wire o_tx;
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`endif
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output reg o_int;
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output reg o_int;
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reg [31:0] nco_step, nco_phase;
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reg [31:0] nco_step;
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// How often shall we create an interrupt? Every reload_value clocks!
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// How often shall we create an interrupt? Every reload_value clocks!
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// at the default reload rate (44.1 kHz, for a 100 MHz clock)
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// at the default reload rate (44.1 kHz, for a 100 MHz clock)
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reg [15:0] reload_value;
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reg [15:0] reload_value;
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| Line 166... |
Line 197... |
// interrupt controller.
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// interrupt controller.
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_int <= (~next_valid);
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o_int <= (~next_valid);
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|
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`ifdef USE_OSERDES
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// If we use an OSERDES on our final output, we should be able to
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// oversample by a factor of 4x (or perhaps more, but this works the
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// 4x number). Here is an example of figuring out what both of those
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// 4x oversamples are--first the primary, calculated as before, but then
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// also the alternate.
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reg [31:0] nco_phase, nco_phase_a, nco_phase_b, nco_phase_c,
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sample_step, tripl_step, tripl_nco_step;
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initial nco_base = 32'h00;
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|
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always @(posedge i_clk)
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if (ztimer)
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sample_step <= nco_step
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+ { {(32-16-5){next_sample[15]}}, next_sample, 5'h00 };
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|
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// Multiply by three ... never that easy
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always @(posedge i_clk)
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tripl_nco_step <= nco_step + { nco_step[30:0], 1'b0 };
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always @(posedge i_clk)
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if (ztimer)
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tripl_step <= tripl_nco_step
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+ { {(32-16-5){next_sample[15]}}, next_sample, 5'h00 };
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+ { {(32-16-6){next_sample[15]}}, next_sample, 6'h00 };
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|
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wire [31:0] base_step;
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assign nco_base_step = sample_step;
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always @(posedge i_clk)
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nco_phase_a <= nco_phase + sample_step;
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always @(posedge i_clk)
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nco_phase_b <= nco_phase + { sample_step[30:0], 1'b0 };
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always @(posedge i_clk)
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nco_phase_c <= nco_phase + tripl_step;
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always @(posedge i_clk)
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nco_phase <= nco_phase + { sample_step[29:0], 2'b00 };
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|
|
// Output a two-bit waveform. Send each bit to GPIO port(s), with
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// roughly the same number of ports per bit.
|
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assign o_tx = { nco_phase_a[31:30], nco_base_b[31:30],
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nco_phase_c[31:30], nco_phase[31:30] };
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`else
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// Adjust the gain for a maximum frequency offset just greater than
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// Adjust the gain for a maximum frequency offset just greater than
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// 75 kHz. (We would've done 75kHz exactly, but it required a multiply
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// 75 kHz. (We would've done 75kHz exactly, but it required a multiply
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// and this doesn't.)
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// and this doesn't.)
|
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reg [31:0] nco_phase;
|
initial nco_phase = 32'h00;
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initial nco_phase = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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nco_phase <= nco_phase + nco_step
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nco_phase <= nco_phase + nco_step
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+ { {(32-16-7){sample_out[15]}}, sample_out, 7'h00 };
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+ { {(32-16-7){sample_out[15]}}, sample_out, 7'h00 };
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assign o_tx = nco_phase[31];
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assign o_tx = nco_phase[31];
|
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`endif
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|
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_addr)
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if (i_wb_addr)
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o_wb_data <= nco_step;
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o_wb_data <= nco_step;
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else
|
else
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