Line 16... |
Line 16... |
axi_cmn: AXI bridges
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axi_cmn: AXI bridges
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fm_hvc: VGA Controller
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fm_hvc: VGA Controller
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synth/zedboard:
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synth/zedboard:
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Vivado project data.
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Vivado project data.
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The data is tested on Vivado v2015.4(64-bit) Windows
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The data is tested on the following Vivado versions,
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v2015.4(64-bit) Windows
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v2016.1(64-bit) Windows
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v2015.2(64-bit) Windows
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v2015.3(64-bit) Windows
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How to Build FPGA Data
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How to Build FPGA Data
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1. Run Vivado Console
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1. Run Vivado Console
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(For example, run the Windows command prompt, then execute settings64.bat
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(For example, run the Windows command prompt, then execute settings64.bat
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Line 35... |
Line 39... |
How to build Xilinx SDK Project
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How to build Xilinx SDK Project
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The following steps import existing demo application projects to Xilinx SDK.
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The following steps import existing demo application projects to Xilinx SDK.
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1. run launch_sdk.tcl. This tcl script imports hardware Specification.
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1. run launch_sdk.tcl. This tcl script imports hardware Specification.
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$vivado -m64 -mode batch -source launch_sdk.tcl
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for Vivado 2015.4
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$vivado -m64 -mode batch -source launch_sdk_2015.4.tcl
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for Vivado 2016.x
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$vivado -m64 -mode batch -source launch_sdk_2016.x.tcl
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2. On the Xilnx SDK Workspace Launcher, set Workspace to
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2. On the Xilnx SDK Workspace Launcher, set Workspace to
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"(your wf3d directry)/implement/synth/zedboard/sdk"
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"(your wf3d directry)/implement/synth/zedboard/sdk"
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3. Generate BSP by default settings
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3. Generate BSP by default settings
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Line 82... |
Line 89... |
$vivado -m64 -mode batch -source load_fpga.tcl
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$vivado -m64 -mode batch -source load_fpga.tcl
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2. On the Xilinx SDK, selsect one project and run the demo.
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2. On the Xilinx SDK, selsect one project and run the demo.
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for example, select simple_cube->right click->
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for example, select simple_cube->right click->
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Run as->Launch on Hardware(System Debugger)
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Run as->Launch on Hardware(System Debugger)
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