| Line 14... |
Line 14... |
set_property target_language Verilog [current_project]
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set_property target_language Verilog [current_project]
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set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
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set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
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set_property vhdl_version vhdl_2k [current_fileset]
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set_property vhdl_version vhdl_2k [current_fileset]
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add_files ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base.bd
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add_files ${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base.bd
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|
|
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# version check
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if {[expr [version -short]] >= 2016.3} {
|
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set PS7 ps7
|
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} else {
|
|
set PS7 processing_system7
|
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}
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|
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set XDC_LIST "\
|
set XDC_LIST "\
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_0_0/zed_base_axi_gpio_0_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0_board.xdc \
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| Line 25... |
Line 32... |
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_1_0/zed_base_axi_gpio_1_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_axi_gpio_2_0/zed_base_axi_gpio_2_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_processing_system7_0_0/zed_base_processing_system7_0_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_processing_system7_0_0/zed_base_processing_system7_0_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_processing_system7_0_50M_0/zed_base_rst_processing_system7_0_50M_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_${PS7}_0_50M_0/zed_base_rst_${PS7}_0_50M_0_board.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_processing_system7_0_50M_0/zed_base_rst_processing_system7_0_50M_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_rst_${PS7}_0_50M_0/zed_base_rst_${PS7}_0_50M_0.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_xbar_0/zed_base_xbar_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_xbar_0/zed_base_xbar_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_auto_pc_0/zed_base_auto_pc_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/ip/zed_base_auto_pc_0/zed_base_auto_pc_0_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base_ooc.xdc \
|
${PROJ_DIR}/${PROJ_NAME}.srcs/sources_1/bd/zed_base/zed_base_ooc.xdc \
|
"
|
"
|
foreach i $XDC_LIST {
|
foreach i $XDC_LIST {
|
