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[/] [wrimm/] [trunk/] [WrimmPackage.vhd] - Diff between revs 3 and 4

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Line 7... Line 7...
        use ieee.std_logic_1164.all;
        use ieee.std_logic_1164.all;
 
 
package WrimmPackage is
package WrimmPackage is
 
 
        constant WbAddrBits             : Integer := 4;
        constant WbAddrBits             : Integer := 4;
        constant WbDataBits             : Integer := 16;
  constant WbDataBits   : Integer := 8;
 
 
        subtype                 WbAddrType      is std_logic_vector(0 to WbAddrBits-1);
        subtype                 WbAddrType      is std_logic_vector(0 to WbAddrBits-1);
        subtype                 WbDataType      is std_logic_vector(0 to WbDataBits-1);
        subtype                 WbDataType      is std_logic_vector(0 to WbDataBits-1);
 
 
        type WbMasterOutType is record
        type WbMasterOutType is record
                Strobe                          : std_logic;                                                                    --Required
                Strobe                          : std_logic;                                                                    --Required
                WrEn                                    : std_logic;
                WrEn                                    : std_logic;
                Addr                                    : WbAddrType;
                Addr                                    : WbAddrType;
                Data                                    : WbDataType;
                Data                                    : WbDataType;
                DataTag                         : std_logic_vector(0 to 1);              --Write,Set,Clear,Toggle
    --DataTag       : std_logic_vector(0 to 1);   --Write,Set,Clear,Toggle
                Cyc                                             : std_logic;                                                                    --Required
                Cyc                                             : std_logic;                                                                    --Required
                CycType                         : std_logic_vector(0 to 2);              --For Burst Cycles
    --CycType       : std_logic_vector(0 to 2);   --For Burst Cycles
        end record WbMasterOutType;
        end record WbMasterOutType;
 
 
        type WbSlaveOutType is record
        type WbSlaveOutType is record
                Ack                                             : std_logic;                                                                    --Required
                Ack                                             : std_logic;                                                                    --Required
                Err                                             : std_logic;
                Err                                             : std_logic;
                Rty                                             : std_logic;
                Rty                                             : std_logic;
                Data                                    : WbDataType;
                Data                                    : WbDataType;
        end record WbSlaveOutType;
        end record WbSlaveOutType;
 
 
        type WbMasterOutArray   is array (natural range <>) of WbMasterOutType;
--=============================================================================
        type WbSlaveOutArray    is array (natural range <>) of WbSlaveOutType;
-------------------------------------------------------------------------------
 
--  Master Interfaces
 
-------------------------------------------------------------------------------
 
  type WbMasterType is (
 
    Q,
 
    P);
 
 
 
  type WbMasterOutArray is array (WbMasterType) of WbMasterOutType;
 
  type WbSlaveOutArray  is array (WbMasterType) of WbSlaveOutType;
 
 
 
  type WbMasterGrantType is Array (WbMasterType'left to WbMasterType'right) of std_logic;
 
--=============================================================================
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
 
--      Status Registers (Report internal results)
--      Status Registers (Report internal results)
--
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
        type StatusFieldParams is record
        type StatusFieldParams is record
                BitWidth        : integer;
                BitWidth        : integer;
                MSBLoc          : integer;
                MSBLoc          : integer;
                Address         : WbAddrType;
                Address         : WbAddrType;
Line 48... Line 56...
        type StatusFieldType     is (
        type StatusFieldType     is (
                StatusA,
                StatusA,
                StatusB,
                StatusB,
                StatusC);
                StatusC);
 
 
        type StatusArrayType                    is Array (StatusFieldType'Left to StatusFieldType'Right)        of WbDataType;
  type StatusArrayType      is Array (StatusFieldType'left to StatusFieldType'right)  of WbDataType;
        type StatusArrayBitType         is Array (StatusFieldType'Left to StatusFieldType'Right)        of std_logic;
  type StatusArrayBitType   is Array (StatusFieldType'left to StatusFieldType'right)  of std_logic;
        type StatusFieldDefType         is Array (StatusFieldType'Left to StatusFieldType'Right)        of StatusFieldParams;
  type StatusFieldDefType   is Array (StatusFieldType'left to StatusFieldType'right)  of StatusFieldParams;
 
 
        constant StatusParams : StatusFieldDefType  :=(
        constant StatusParams : StatusFieldDefType  :=(
                StatusA                                         => (BitWidth => 16, MSBLoc =>  0, Address => x"0"),
    StatusA           => (BitWidth =>  8, MSBLoc =>  0, Address => x"0"),
                StatusB                                         => (BitWidth =>  8, MSBLoc =>  0, Address => x"1"),
                StatusB                                         => (BitWidth =>  8, MSBLoc =>  0, Address => x"1"),
                StatusC                                         => (BitWidth =>  4, MSBLoc => 12, Address => x"2"));
    StatusC           => (BitWidth =>  8, MSBLoc =>  0, Address => x"2"));
 
--=============================================================================
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
 
--      Setting Registers
--      Setting Registers
--
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
        type SettingFieldParams is record
        type SettingFieldParams is record
                BitWidth        : integer;
                BitWidth        : integer;
                MSBLoc          : integer;
                MSBLoc          : integer;
                Address         : WbAddrType;
                Address         : WbAddrType;
Line 78... Line 85...
        type SettingArrayType                   is Array (SettingFieldType'Left to SettingFieldType'Right)      of WbDataType;
        type SettingArrayType                   is Array (SettingFieldType'Left to SettingFieldType'Right)      of WbDataType;
        type SettingArrayBitType        is Array (SettingFieldType'Left to SettingFieldType'Right)      of std_logic;
        type SettingArrayBitType        is Array (SettingFieldType'Left to SettingFieldType'Right)      of std_logic;
        type SettingFieldDefType        is Array (SettingFieldType'Left to SettingFieldType'Right)      of SettingFieldParams;
        type SettingFieldDefType        is Array (SettingFieldType'Left to SettingFieldType'Right)      of SettingFieldParams;
 
 
        constant SettingParams : SettingFieldDefType  :=(
        constant SettingParams : SettingFieldDefType  :=(
                SettingX                => (BitWidth => 32, MSBLoc =>  0, Address => x"62", Default => x"0000"),
    SettingX    => (BitWidth => 8, MSBLoc =>  0, Address => x"6", Default => x"00"),
                SettingY                => (BitWidth => 32, MSBLoc =>  0, Address => x"64", Default => x"0000"),
    SettingY    => (BitWidth => 8, MSBLoc =>  0, Address => x"7", Default => x"00"),
                SettingZ                => (BitWidth =>  1, MSBLoc => 31, Address => x"67", Default => x"0000"));
    SettingZ    => (BitWidth => 8, MSBLoc =>  0, Address => x"8", Default => x"00"));
 
--=============================================================================
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
 
--      Trigger Registers (Report internal results)
--      Trigger Registers (Report internal results)
--
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
        type TriggerFieldParams is record
        type TriggerFieldParams is record
                BitLoc          : integer;
                BitLoc          : integer;
                Address         : WbAddrType;
                Address         : WbAddrType;
  end record TriggerFieldParams;
  end record TriggerFieldParams;
Line 101... Line 106...
 
 
        type TriggerArrayType                   is Array (TriggerFieldType'Left to TriggerFieldType'Right)      of std_logic;
        type TriggerArrayType                   is Array (TriggerFieldType'Left to TriggerFieldType'Right)      of std_logic;
        type TriggerFieldDefType        is Array (TriggerFieldType'Left to TriggerFieldType'Right)      of TriggerFieldParams;
        type TriggerFieldDefType        is Array (TriggerFieldType'Left to TriggerFieldType'Right)      of TriggerFieldParams;
 
 
        constant TriggerParams : TriggerFieldDefType :=(
        constant TriggerParams : TriggerFieldDefType :=(
                TriggerR                        => (BitLoc => 31, Address => x"6"),
    TriggerR      => (BitLoc => 7, Address => x"A"),
                TriggerS                        => (BitLoc => 31, Address => x"8"),
    TriggerS      => (BitLoc => 7, Address => x"B"),
                TriggerT                        => (BitLoc => 31, Address => x"8"));
    TriggerT      => (BitLoc => 7, Address => x"C"));
 
 
end package WrimmPackage;
end package WrimmPackage;
 
 
--package body WishBonePackage is
--package body WishBonePackage is
--
--

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