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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_fifo_ctrl.v] - Diff between revs 7 and 11

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Rev 7	Rev 11
Line 100...	Line 100...
`reg [AWIDTH:0] next_rd_ptr;`	`reg [AWIDTH:0] next_rd_ptr;`

`// Combinatorial`	`// Combinatorial`

`wire [AWIDTH:0] wr_gray;`	`wire [AWIDTH:0] wr_gray;`
	`reg [AWIDTH:0] wr_gray_reg;`
`reg [AWIDTH:0] wr_gray_meta;`	`reg [AWIDTH:0] wr_gray_meta;`
`reg [AWIDTH:0] wr_gray_sync;`	`reg [AWIDTH:0] wr_gray_sync;`
`reg [AWIDTH:0] wck_rd_ptr;`	`reg [AWIDTH:0] wck_rd_ptr;`
`wire [AWIDTH:0] wck_level;`	`wire [AWIDTH:0] wck_level;`

`wire [AWIDTH:0] rd_gray;`	`wire [AWIDTH:0] rd_gray;`
	`reg [AWIDTH:0] rd_gray_reg;`
`reg [AWIDTH:0] rd_gray_meta;`	`reg [AWIDTH:0] rd_gray_meta;`
`reg [AWIDTH:0] rd_gray_sync;`	`reg [AWIDTH:0] rd_gray_sync;`
`reg [AWIDTH:0] rck_wr_ptr;`	`reg [AWIDTH:0] rck_wr_ptr;`
`wire [AWIDTH:0] rck_level;`	`wire [AWIDTH:0] rck_level;`

Line 200...	Line 202...

`// Instantiate metastability flops`	`// Instantiate metastability flops`
`always @(posedge rclk or negedge rrst_n)`	`always @(posedge rclk or negedge rrst_n)`
`begin`	`begin`
`if (!rrst_n) begin`	`if (!rrst_n) begin`
	`rd_gray_reg <= {(AWIDTH+1){1'b0}};`
`wr_gray_meta <= {(AWIDTH+1){1'b0}};`	`wr_gray_meta <= {(AWIDTH+1){1'b0}};`
`wr_gray_sync <= {(AWIDTH+1){1'b0}};`	`wr_gray_sync <= {(AWIDTH+1){1'b0}};`
`end`	`end`
`else begin`	`else begin`
`wr_gray_meta <= wr_gray;`	`rd_gray_reg <= rd_gray;`
	`wr_gray_meta <= wr_gray_reg;`
`wr_gray_sync <= wr_gray_meta;`	`wr_gray_sync <= wr_gray_meta;`
`end`	`end`
`end`	`end`

`always @(posedge wclk or negedge wrst_n)`	`always @(posedge wclk or negedge wrst_n)`
`begin`	`begin`
`if (!wrst_n) begin`	`if (!wrst_n) begin`
	`wr_gray_reg <= {(AWIDTH+1){1'b0}};`
`rd_gray_meta <= {(AWIDTH+1){1'b0}};`	`rd_gray_meta <= {(AWIDTH+1){1'b0}};`
`rd_gray_sync <= {(AWIDTH+1){1'b0}};`	`rd_gray_sync <= {(AWIDTH+1){1'b0}};`
`end`	`end`
`else begin`	`else begin`
`rd_gray_meta <= rd_gray;`	`wr_gray_reg <= wr_gray;`
	`rd_gray_meta <= rd_gray_reg;`
`rd_gray_sync <= rd_gray_meta;`	`rd_gray_sync <= rd_gray_meta;`
`end`	`end`
`end`	`end`
`end`	`end`
`else begin`	`else begin`
Line 264...	Line 270...
`end`	`end`
`endgenerate`	`endgenerate`

`endmodule`	`endmodule`




`No newline at end of file`	`No newline at end of file`

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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_fifo_ctrl.v] - Diff between revs 7 and 11