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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_small.v] - Diff between revs 20 and 21
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| Rev 20 |
Rev 21 |
| Line 85... |
Line 85... |
// Local declarations
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// Local declarations
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// Registers
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// Registers
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reg [DWIDTH-1:0] mem_rdata;
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reg [DWIDTH-1:0] mem_rdata;
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reg [AWIDTH-1:0] raddr_d1;
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// Memory
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// Memory
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reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
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reg [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
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| Line 111... |
Line 112... |
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//---
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//---
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// Memory Read
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// Memory Read
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// Generate registered memory read
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// Generate registered memory read
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`ifdef XIL
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//always @(posedge rclk)
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//begin
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// if (ren) begin
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// raddr_d1 <= raddr;
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// end
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//end
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//always @(raddr_d1, rclk)
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//begin
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// mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
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//end
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always @(posedge rclk)
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begin
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if (!rrst_n) begin
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mem_rdata <= {(DWIDTH){1'b0}};
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end else if (ren) begin
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mem_rdata <= mem[raddr[AWIDTH-1:0]];
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end
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end
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`else
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always @(posedge rclk or negedge rrst_n)
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always @(posedge rclk or negedge rrst_n)
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begin
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begin
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if (!rrst_n) begin
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if (!rrst_n) begin
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mem_rdata <= {(DWIDTH){1'b0}};
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mem_rdata <= {(DWIDTH){1'b0}};
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end else if (ren) begin
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end else if (ren) begin
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mem_rdata <= mem[raddr[AWIDTH-1:0]];
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mem_rdata <= mem[raddr[AWIDTH-1:0]];
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end
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end
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end
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end
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`endif
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generate
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generate
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if (REGISTER_READ) begin
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if (REGISTER_READ) begin
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// Generate registered output
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// Generate registered output
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always @(posedge rclk or negedge rrst_n)
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always @(posedge rclk or negedge rrst_n)
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