| Line 40... |
Line 40... |
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module tx_dequeue(/*AUTOARG*/
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module tx_dequeue(/*AUTOARG*/
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// Outputs
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// Outputs
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txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
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txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
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txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
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txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
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status_good_frame_tx_tog, status_good_frame_tx_size,
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txsfifo_wen, txsfifo_wdata,
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// Inputs
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// Inputs
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clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
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clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
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status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
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status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
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txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
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txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
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txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
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txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
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| Line 86... |
Line 86... |
output [63:0] xgmii_txd;
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output [63:0] xgmii_txd;
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output [7:0] xgmii_txc;
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output [7:0] xgmii_txc;
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output status_txdfifo_udflow_tog;
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output status_txdfifo_udflow_tog;
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output status_good_frame_tx_tog;
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output txsfifo_wen;
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output [13:0] status_good_frame_tx_size;
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output [13:0] txsfifo_wdata;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [13:0] status_good_frame_tx_size;
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reg status_good_frame_tx_tog;
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reg status_txdfifo_udflow_tog;
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reg status_txdfifo_udflow_tog;
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reg txdfifo_ren;
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reg txdfifo_ren;
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reg txhfifo_ren;
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reg txhfifo_ren;
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reg [63:0] txhfifo_wdata;
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reg [63:0] txhfifo_wdata;
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reg txhfifo_wen;
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reg txhfifo_wen;
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reg [7:0] txhfifo_wstatus;
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reg [7:0] txhfifo_wstatus;
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reg [13:0] txsfifo_wdata;
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reg txsfifo_wen;
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reg [7:0] xgmii_txc;
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reg [7:0] xgmii_txc;
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reg [63:0] xgmii_txd;
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reg [63:0] xgmii_txd;
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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Line 249... |
xgxs_txd <= {8{`IDLE}};
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xgxs_txd <= {8{`IDLE}};
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xgxs_txc <= 8'hff;
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xgxs_txc <= 8'hff;
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status_txdfifo_udflow_tog <= 1'b0;
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status_txdfifo_udflow_tog <= 1'b0;
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status_good_frame_tx_tog <= 1'b0;
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txsfifo_wen <= 1'b0;
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status_good_frame_tx_size <= 14'b0;
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txsfifo_wdata <= 14'b0;
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end
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end
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else begin
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else begin
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curr_state_enc <= next_state_enc;
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curr_state_enc <= next_state_enc;
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Line 272... |
xgxs_txd_barrel <= next_xgxs_txd[63:32];
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xgxs_txd_barrel <= next_xgxs_txd[63:32];
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xgxs_txc_barrel <= next_xgxs_txc[7:4];
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xgxs_txc_barrel <= next_xgxs_txc[7:4];
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frame_available <= next_frame_available;
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frame_available <= next_frame_available;
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txsfifo_wen <= 1'b0;
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txsfifo_wdata <= byte_cnt;
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//---
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//---
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// Barrel shifter. Previous stage always align packet with LANE0.
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// Barrel shifter. Previous stage always align packet with LANE0.
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// This stage allow us to shift packet to align with LANE4 if needed
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// This stage allow us to shift packet to align with LANE4 if needed
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// for correct inter frame gap (IFG).
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// for correct inter frame gap (IFG).
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Line 304... |
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//---
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//---
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// Frame count and size
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// Frame count and size
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if (frame_end) begin
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if (frame_end) begin
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status_good_frame_tx_tog <= ~status_good_frame_tx_tog;
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txsfifo_wen <= 1'b1;
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status_good_frame_tx_size <= byte_cnt;
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end
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end
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end
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end
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end
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end
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