URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [wishbone_if.v] - Diff between revs 7 and 12

Rev 7	Rev 12
Line 40...	Line 40...

`module wishbone_if(/AUTOARG/`	`module wishbone_if(/AUTOARG/`
`// Outputs`	`// Outputs`
`wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,`	`wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,`
`// Inputs`	`// Inputs`
`wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i,`	`wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,`
`wb_cyc_i, status_crc_error, status_fragment_error,`	`status_crc_error, status_fragment_error, status_txdfifo_ovflow,`
`status_txdfifo_ovflow, status_txdfifo_udflow,`	`status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,`
`status_rxdfifo_ovflow, status_rxdfifo_udflow,`
`status_pause_frame_rx, status_local_fault, status_remote_fault`	`status_pause_frame_rx, status_local_fault, status_remote_fault`
`);`	`);`


`input wb_clk_i;`	`input wb_clk_i;`
Line 97...	Line 96...
`reg status_remote_fault_d1;`	`reg status_remote_fault_d1;`
`reg status_local_fault_d1;`	`reg status_local_fault_d1;`


`/AUTOWIRE/`	`/AUTOWIRE/`
`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
`// End of automatics`

`wire [8:0] int_sources;`	`wire [8:0] int_sources;`


`//---`	`//---`