| Line 42... |
Line 42... |
// Outputs
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// Outputs
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wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable, clear_stats_tx_octets,
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wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable, clear_stats_tx_octets,
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clear_stats_tx_pkts, clear_stats_rx_octets, clear_stats_rx_pkts,
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clear_stats_tx_pkts, clear_stats_rx_octets, clear_stats_rx_pkts,
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// Inputs
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// Inputs
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
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status_crc_error, status_fragment_error, status_txdfifo_ovflow,
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status_crc_error, status_fragment_error, status_lenght_error,
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status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
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status_txdfifo_ovflow, status_txdfifo_udflow, status_rxdfifo_ovflow,
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status_pause_frame_rx, status_local_fault, status_remote_fault,
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status_rxdfifo_udflow, status_pause_frame_rx, status_local_fault,
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stats_tx_octets, stats_tx_pkts, stats_rx_octets, stats_rx_pkts
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status_remote_fault, stats_tx_octets, stats_tx_pkts,
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stats_rx_octets, stats_rx_pkts
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);
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);
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|
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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| Line 64... |
Line 65... |
output wb_ack_o;
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output wb_ack_o;
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output wb_int_o;
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output wb_int_o;
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|
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input status_crc_error;
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input status_crc_error;
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input status_fragment_error;
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input status_fragment_error;
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input status_lenght_error;
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|
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input status_txdfifo_ovflow;
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input status_txdfifo_ovflow;
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|
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input status_txdfifo_udflow;
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input status_txdfifo_udflow;
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|
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| Line 107... |
Line 109... |
reg next_wb_int_o;
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reg next_wb_int_o;
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|
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reg [0:0] cpureg_config0;
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reg [0:0] cpureg_config0;
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reg [0:0] next_cpureg_config0;
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reg [0:0] next_cpureg_config0;
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|
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reg [8:0] cpureg_int_pending;
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reg [9:0] cpureg_int_pending;
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reg [8:0] next_cpureg_int_pending;
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reg [9:0] next_cpureg_int_pending;
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|
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reg [8:0] cpureg_int_mask;
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reg [9:0] cpureg_int_mask;
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reg [8:0] next_cpureg_int_mask;
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reg [9:0] next_cpureg_int_mask;
|
|
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reg cpuack;
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reg cpuack;
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reg next_cpuack;
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reg next_cpuack;
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|
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reg status_remote_fault_d1;
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reg status_remote_fault_d1;
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reg status_local_fault_d1;
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reg status_local_fault_d1;
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|
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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|
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wire [8:0] int_sources;
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wire [9:0] int_sources;
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|
|
|
|
//---
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//---
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// Source of interrupts, some are edge sensitive, others
|
// Source of interrupts, some are edge sensitive, others
|
// expect a pulse signal.
|
// expect a pulse signal.
|
|
|
assign int_sources = {
|
assign int_sources = {
|
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status_lenght_error,
|
status_fragment_error,
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status_fragment_error,
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status_crc_error,
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status_crc_error,
|
|
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status_pause_frame_rx,
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status_pause_frame_rx,
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|
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| Line 192... |
Line 195... |
`CPUREG_CONFIG0: begin
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`CPUREG_CONFIG0: begin
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next_wb_dat_o = {31'b0, cpureg_config0};
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next_wb_dat_o = {31'b0, cpureg_config0};
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end
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end
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|
|
`CPUREG_INT_PENDING: begin
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`CPUREG_INT_PENDING: begin
|
next_wb_dat_o = {23'b0, cpureg_int_pending};
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next_wb_dat_o = {22'b0, cpureg_int_pending};
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next_cpureg_int_pending = int_sources;
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next_cpureg_int_pending = int_sources;
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next_wb_int_o = 1'b0;
|
next_wb_int_o = 1'b0;
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end
|
end
|
|
|
`CPUREG_INT_STATUS: begin
|
`CPUREG_INT_STATUS: begin
|
next_wb_dat_o = {23'b0, int_sources};
|
next_wb_dat_o = {22'b0, int_sources};
|
end
|
end
|
|
|
`CPUREG_INT_MASK: begin
|
`CPUREG_INT_MASK: begin
|
next_wb_dat_o = {23'b0, cpureg_int_mask};
|
next_wb_dat_o = {22'b0, cpureg_int_mask};
|
end
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end
|
|
|
`CPUREG_STATSTXOCTETS: begin
|
`CPUREG_STATSTXOCTETS: begin
|
next_wb_dat_o = stats_tx_octets;
|
next_wb_dat_o = stats_tx_octets;
|
clear_stats_tx_octets = 1'b1;
|
clear_stats_tx_octets = 1'b1;
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| Line 244... |
Line 247... |
`CPUREG_CONFIG0: begin
|
`CPUREG_CONFIG0: begin
|
next_cpureg_config0 = wb_dat_i[0:0];
|
next_cpureg_config0 = wb_dat_i[0:0];
|
end
|
end
|
|
|
`CPUREG_INT_PENDING: begin
|
`CPUREG_INT_PENDING: begin
|
next_cpureg_int_pending = wb_dat_i[8:0] | cpureg_int_pending | int_sources;
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next_cpureg_int_pending = wb_dat_i[9:0] | cpureg_int_pending | int_sources;
|
end
|
end
|
|
|
`CPUREG_INT_MASK: begin
|
`CPUREG_INT_MASK: begin
|
next_cpureg_int_mask = wb_dat_i[8:0];
|
next_cpureg_int_mask = wb_dat_i[9:0];
|
end
|
end
|
|
|
default: begin
|
default: begin
|
end
|
end
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|
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| Line 265... |
Line 268... |
always @(posedge wb_clk_i or posedge wb_rst_i) begin
|
always @(posedge wb_clk_i or posedge wb_rst_i) begin
|
|
|
if (wb_rst_i == 1'b1) begin
|
if (wb_rst_i == 1'b1) begin
|
|
|
cpureg_config0 <= 1'h1;
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cpureg_config0 <= 1'h1;
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cpureg_int_pending <= 9'b0;
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cpureg_int_pending <= 10'b0;
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cpureg_int_mask <= 9'b0;
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cpureg_int_mask <= 10'b0;
|
|
|
wb_dat_o <= 32'b0;
|
wb_dat_o <= 32'b0;
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wb_int_o <= 1'b0;
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wb_int_o <= 1'b0;
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|
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cpuack <= 1'b0;
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cpuack <= 1'b0;
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