URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [sim/] [verilog/] [sim.do] - Diff between revs 17 and 23

Rev 17	Rev 23
Line 36...	Line 36...

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/tx_enqueue.v`

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/wishbone_if.v`

	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/stats.v`

`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../rtl/verilog/xge_mac.v`



`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.sv`	`vlog -timescale 1ps/1ps +incdir+../../rtl/include ../../tbench/verilog/tb_xge_mac.sv`
Line 84...	Line 86...

`add wave sim:/tb/dut/fault_sm0/*`	`add wave sim:/tb/dut/fault_sm0/*`

`add wave -divider`	`add wave -divider`

	`add wave sim:/tb/dut/stats0/*`

	`add wave -divider`

`add wave sim:/tb/dut/wishbone_if0/*`	`add wave sim:/tb/dut/wishbone_if0/*`


`#run 1000ns`	`#run 1000ns`