URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [RAM.vhdl] - Diff between revs 20 and 25

Rev 20	Rev 25
Line 48...	Line 48...

`LIBRARY ieee;`	`LIBRARY ieee;`
`USE ieee.std_logic_1164.ALL;`	`USE ieee.std_logic_1164.ALL;`
`USE ieee.numeric_std.ALL;`	`USE ieee.numeric_std.ALL;`
`USE work.ram_parts.ALL;`	`USE work.ram_parts.ALL;`
	`USE work.hexio.ALL;`

`ENTITY memory IS`	`ENTITY memory IS`

`-- Memory component based upon Xilinx Spartan-6 block RAM`	`-- Memory component based upon Xilinx Spartan-6 block RAM`
`-- Maximum capacity is 16k words`	`-- Maximum capacity is 16k words`
Line 73...	Line 74...

`END memory;`	`END memory;`

`ARCHITECTURE Structural OF memory IS`	`ARCHITECTURE Structural OF memory IS`

	`CONSTANT dummy : INTEGER := notify_f("Initialisation of memory component starts");`

`BEGIN -- Structural`	`BEGIN -- Structural`

`SMALL_MEM : IF w_data >= 8 AND w_data <= 14 GENERATE`	`SMALL_MEM : IF w_addr >= 8 AND w_addr <= 14 GENERATE`
`MEM0 : RAM_GENERIC`	`MEM0 : RAM_GENERIC`
`GENERIC MAP (`	`GENERIC MAP (`
`filename => filename,`	`filename => filename,`
`w_data => w_data,`	`w_data => w_data,`
`w_addr => w_addr)`	`w_addr => w_addr)`
Line 91...	Line 94...
`d1 => d1,`	`d1 => d1,`
`q1 => q1,`	`q1 => q1,`
`q2 => q2);`	`q2 => q2);`
`END GENERATE SMALL_MEM;`	`END GENERATE SMALL_MEM;`

`LARGE_MEM : IF w_data = 15 GENERATE`	`LARGE_MEM : IF w_addr = 15 GENERATE`
`MEM1: RAM32K`	`MEM1: RAM32K`
`GENERIC MAP (`	`GENERIC MAP (`
`filename => filename,`	`filename => filename,`
`w_data => w_data)`	`w_data => w_data)`
`PORT MAP (`	`PORT MAP (`