URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [tb_generic_ram.vhdl] - Diff between revs 20 and 23
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 20 |
Rev 23 |
| Line 28... |
Line 28... |
ENTITY tb_generic_ram IS
|
ENTITY tb_generic_ram IS
|
END ENTITY tb_generic_ram;
|
END ENTITY tb_generic_ram;
|
|
|
ARCHITECTURE Structural OF tb_generic_ram IS
|
ARCHITECTURE Structural OF tb_generic_ram IS
|
|
|
CONSTANT w_addr : INTEGER := 15;
|
CONSTANT w_addr : INTEGER := 10;
|
|
|
SIGNAL clock : STD_LOGIC := '0';
|
SIGNAL clock : STD_LOGIC := '0';
|
SIGNAL we : STD_LOGIC := '0';
|
SIGNAL we : STD_LOGIC := '0';
|
SIGNAL data_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0) := (OTHERS => '0');
|
SIGNAL data_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0) := (OTHERS => '0');
|
SIGNAL inst_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
|
SIGNAL inst_a : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
