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[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [tb_generic_ram.vhdl] - Diff between revs 23 and 25
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Rev 25 |
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Line 19... |
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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USE work.RAM.ALL;
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USE work.RAM.ALL;
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USE work.hexio.ALL;
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-- Test bench for instatiating a memory and initialising
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-- Test bench for instatiating a memory and initialising
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-- it from a file.
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-- it from a file.
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ENTITY tb_generic_ram IS
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ENTITY tb_generic_ram IS
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SIGNAL data_i : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_i : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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SIGNAL data_o : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL data_o : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL inst_o : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL inst_o : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL ctr_a : NATURAL RANGE 0 TO (2**w_addr - 1);
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SIGNAL ctr_a : NATURAL RANGE 0 TO (2**w_addr - 1);
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CONSTANT dummy : INTEGER := notify_f("Initialising tb_generic_ram");
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BEGIN -- ARCHITECTURE Structural
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BEGIN -- ARCHITECTURE Structural
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-- purpose: Data dumping when simulation starts
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-- type : combinational
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-- inputs :
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-- outputs:
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dump1: PROCESS IS
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BEGIN -- PROCESS dump1
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notify("Simulation of tb_generic_ram starts");
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WAIT;
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END PROCESS dump1;
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RAM1 : memory
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RAM1 : memory
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GENERIC MAP (
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GENERIC MAP (
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filename => "test_data.txt",
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filename => "test_data.txt",
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w_addr => w_addr)
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w_addr => w_addr)
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PORT MAP (
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PORT MAP (
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