| Line 19... |
Line 19... |
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LIBRARY IEEE;
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE IEEE.numeric_std.ALL;
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USE work.components.ALL;
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USE work.components.ALL;
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USE work.ram_parts.ALL;
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USE work.RAM.ALL;
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USE work.mux_parts.ALL;
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USE work.mux_parts.ALL;
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USE work.controllers.ALL;
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USE work.controllers.ALL;
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-- LIBRARY unisim;
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-- LIBRARY unisim;
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-- USE unisim.vcomponents.ALL;
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-- USE unisim.vcomponents.ALL;
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| Line 38... |
Line 38... |
END system;
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END system;
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ARCHITECTURE Structural OF system IS
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ARCHITECTURE Structural OF system IS
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CONSTANT w_data : POSITIVE := 16;
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CONSTANT w_data : POSITIVE := 16;
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CONSTANT w_addr : POSITIVE := 11;
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SIGNAL CLK : STD_LOGIC; -- System clock
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SIGNAL CLK : STD_LOGIC; -- System clock
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SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
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SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
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SIGNAL RST : STD_LOGIC; -- System synchronous reset
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SIGNAL RST : STD_LOGIC; -- System synchronous reset
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| Line 295... |
Line 296... |
CLK => CLK,
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CLK => CLK,
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ena => EIN2,
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ena => EIN2,
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Q => DO3,
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Q => DO3,
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port_in => pushb_in);
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port_in => pushb_in);
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-- 1kx16 two port RAM
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-- 32kx16 two port RAM
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MEM1 : generic_ram
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MEM1 : memory
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GENERIC MAP (
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GENERIC MAP (
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filename => "input_data.txt",
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w_data => w_data,
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w_addr => 11)
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w_addr => w_addr,
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filename => "")
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PORT MAP (
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PORT MAP (
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CLK => CLK,
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CLK => CLK,
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we => MEM_WR,
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we => MEM_WR,
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a1 => B_OUT(10 DOWNTO 0),
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a1 => B_OUT(w_addr - 1 DOWNTO 0),
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a2 => PC_NEXT(10 DOWNTO 0),
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a2 => PC_NEXT(w_addr - 1 DOWNTO 0),
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d1 => A_OUT,
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d1 => A_OUT,
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q1 => MEMO4, -- Data memory output
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q1 => MEMO4, -- Data memory output
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q2 => INSO4); -- Instruction memory output
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q2 => INSO4); -- Instruction memory output
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IR : data_reg
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IR : data_reg
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