URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [rtl/] [cpu/] [idecode.v] - Diff between revs 113 and 118

Rev 113	Rev 118
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`// Filename: idecode.v`	`// Filename: idecode.v`
`//`	`//`
`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`	`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
`//`	`//`
`// Purpose: This RTL file specifies how instructions are to be decoded`	`// Purpose: This RTL file specifies how instructions are to be decoded`
`// into their underlying meanings. This is specifically a version`	`// into their underlying meanings.`
`// designed to support a "Next Generation", or "Version 2" instruction`
`// set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option`
`// in cpudefs.v.`
`//`
`// I expect to (eventually) retire the old instruction set, at which point`
`// this will become the default instruction set decoder.`
`//`	`//`
`//`	`//`
`// Creator: Dan Gisselquist, Ph.D.`	`// Creator: Dan Gisselquist, Ph.D.`
`// Gisselquist Technology, LLC`	`// Gisselquist Technology, LLC`
`//`	`//`