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[/] [xulalx25soc/] [trunk/] [rtl/] [txuart.v] - Diff between revs 99 and 113

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Rev 99 Rev 113
Line 165... Line 165...
                end else if (state == `TXU_IDLE)        // STATE_IDLE
                end else if (state == `TXU_IDLE)        // STATE_IDLE
                begin
                begin
                        // baud_counter <= 0;
                        // baud_counter <= 0;
                        r_setup <= i_setup;
                        r_setup <= i_setup;
                        calc_parity <= 1'b0;
                        calc_parity <= 1'b0;
 
                        lcl_data <= i_data;
                        if ((i_wr)&&(~r_busy))
                        if ((i_wr)&&(~r_busy))
                        begin   // Immediately start us off with a start bit
                        begin   // Immediately start us off with a start bit
                                o_uart <= 1'b0;
                                o_uart <= 1'b0;
                                r_busy <= 1'b1;
                                r_busy <= 1'b1;
                                case(data_bits)
                                case(data_bits)
                                2'b00: state <= `TXU_BIT_ZERO;
                                2'b00: state <= `TXU_BIT_ZERO;
                                2'b01: state <= `TXU_BIT_ONE;
                                2'b01: state <= `TXU_BIT_ONE;
                                2'b10: state <= `TXU_BIT_TWO;
                                2'b10: state <= `TXU_BIT_TWO;
                                2'b11: state <= `TXU_BIT_THREE;
                                2'b11: state <= `TXU_BIT_THREE;
                                endcase
                                endcase
                                lcl_data <= i_data;
 
                                // baud_counter <= clocks_per_baud-28'h01;
                                // baud_counter <= clocks_per_baud-28'h01;
                        end else begin // Stay in idle
                        end else begin // Stay in idle
                                o_uart <= 1'b1;
                                o_uart <= 1'b1;
                                r_busy <= 0;
                                r_busy <= 0;
                                // lcl_data is irrelevant
 
                                // state <= state;
                                // state <= state;
                        end
                        end
                end else begin
                end else begin
                        // One clock tick in each of these states ...
                        // One clock tick in each of these states ...
                        // baud_counter <= clocks_per_baud - 28'h01;
                        // baud_counter <= clocks_per_baud - 28'h01;
Line 225... Line 224...
        end
        end
 
 
        assign  o_busy = (r_busy);
        assign  o_busy = (r_busy);
 
 
 
 
        initial zero_baud_counter = 1'b0;
        initial zero_baud_counter = 1'b1;
 
        initial baud_counter = 28'd80000; // 1ms
        always @(posedge i_clk)
        always @(posedge i_clk)
        begin
        begin
                zero_baud_counter <= (baud_counter == 28'h01);
                zero_baud_counter <= (baud_counter == 28'h01);
                if ((i_reset)||(i_break))
                if ((i_reset)||(i_break))
                        // Give ourselves 16 bauds before being ready
                        // Give ourselves 16 bauds before being ready

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