Subversion Repositories xulalx25soc

        reg     [29:0]   r_setup;

        reg     [29:0]   r_setup;

        reg             r_tx_stb, rx_rdy;

        reg             r_tx_stb, rx_rdy;

        reg     [7:0]    r_tx_data;

        reg     [7:0]    r_tx_data;

        initial r_setup = DEFAULT_SETUP;

        initial r_setup = DEFAULT_SETUP;

        always @(posedge i_clk)

        always @(posedge i_clk)

                        r_setup <= i_wb_data[29:0];

                        r_setup <= i_wb_data[29:0];

        initial r_tx_stb = 1'b0;

        initial r_tx_stb = 1'b0;

        always @(posedge i_clk)

        always @(posedge i_clk)

                begin

                begin

                        // Note: there's no check for overflow here.

                        // Note: there's no check for overflow here.

                        // You're on your own: verify that the device

                        // You're on your own: verify that the device

                        // isn't busy first.

                        // isn't busy first.

                        r_tx_data <= i_wb_data[7:0];

                        r_tx_data <= i_wb_data[7:0];

                case(i_wb_addr)

                case(i_wb_addr)

                2'b00: o_wb_data <= { 2'b00, r_setup };

                2'b00: o_wb_data <= { 2'b00, r_setup };

                2'b01: o_wb_data <= { 2'b00, r_setup };

                2'b01: o_wb_data <= { 2'b00, r_setup };

                2'b10: begin

                2'b10: begin

                                rx_rdy <= rx_stb;

                                rx_rdy <= rx_stb;

                        o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };

                        o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };

                        end

                        end

                2'b11: o_wb_data <= { 31'h00,tx_busy };

                2'b11: o_wb_data <= { 31'h00,tx_busy };

                endcase

                endcase

        end

        end

        assign  o_wb_stall = 1'b0;

        assign  o_wb_stall = 1'b0;

        assign  o_rx_int = rx_stb;

        assign  o_rx_int = rx_stb;

        assign  o_tx_int = ~tx_busy;

        assign  o_tx_int = ~tx_busy;