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Line 40... |
input i_clk, i_stb;
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input i_clk, i_stb;
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input [35:0] i_word;
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input [35:0] i_word;
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output reg o_stb;
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output reg o_stb;
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output reg [35:0] o_word;
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output reg [35:0] o_word;
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// Clock zero
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// { o_stb, r_stb } = 0
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wire cmd_write_not_compressed = (i_word[35:33] == 3'h3);
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wire cmd_write_not_compressed = (i_word[35:33] == 3'h3);
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// Clock one: { o_stb, r_stb } = 4'h1 when done
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reg [7:0] wr_addr;
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reg [7:0] wr_addr;
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initial wr_addr = 8'h0;
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initial wr_addr = 8'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_stb)&&(cmd_write_not_compressed))
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if ((i_stb)&&(cmd_write_not_compressed))
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wr_addr <= wr_addr + 8'h1;
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wr_addr <= wr_addr + 8'h1;
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reg [31:0] compression_tbl [0:255];
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reg [31:0] compression_tbl [0:255];
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always @(posedge i_clk)
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always @(posedge i_clk)
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compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
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compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
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// Clock 0, calculate the table address ... 1 is the smallest address
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reg [35:0] r_word;
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wire [7:0] cmd_addr;
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always @(posedge i_clk)
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assign cmd_addr = wr_addr - { i_word[32:31], i_word[29:24] };
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r_word <= i_word;
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// Clock one, read the table value
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// Clock two, calculate the table address ... 1 is the smallest address
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reg [31:0] cword;
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// { o_stb, r_stb } = 4'h2 when done
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reg [7:0] cmd_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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cword <= compression_tbl[cmd_addr];
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cmd_addr = wr_addr - { r_word[32:31], r_word[29:24] };
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// Let's also calculate the address, in case this is a compressed
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// Let's also calculate the address, in case this is a compressed
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// address word
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// address word
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reg [24:0] r_addr;
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reg [24:0] r_addr;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_word[32:30])
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case(r_word[32:30])
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3'b000: r_addr <= { 19'h0, i_word[29:24] };
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3'b000: r_addr <= { 19'h0, r_word[29:24] };
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3'b010: r_addr <= { 13'h0, i_word[29:18] };
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3'b010: r_addr <= { 13'h0, r_word[29:18] };
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3'b100: r_addr <= { 7'h0, i_word[29:12] };
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3'b100: r_addr <= { 7'h0, r_word[29:12] };
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3'b110: r_addr <= { 1'h0, i_word[29: 6] };
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3'b110: r_addr <= { 1'h0, r_word[29: 6] };
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3'b001: r_addr <= { {(19){ i_word[29]}}, i_word[29:24] };
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3'b001: r_addr <= { {(19){ r_word[29]}}, r_word[29:24] };
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3'b011: r_addr <= { {(13){ i_word[29]}}, i_word[29:18] };
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3'b011: r_addr <= { {(13){ r_word[29]}}, r_word[29:18] };
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3'b101: r_addr <= { {( 7){ i_word[29]}}, i_word[29:12] };
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3'b101: r_addr <= { {( 7){ r_word[29]}}, r_word[29:12] };
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3'b111: r_addr <= { {( 1){ i_word[29]}}, i_word[29: 6] };
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3'b111: r_addr <= { {( 1){ r_word[29]}}, r_word[29: 6] };
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endcase
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endcase
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wire [31:0] w_addr;
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wire [31:0] w_addr;
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assign w_addr = { {(7){r_addr[24]}}, r_addr };
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assign w_addr = { {(7){r_addr[24]}}, r_addr };
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reg [9:0] rd_len;
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reg [9:0] rd_len;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (~i_word[34])
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if (~r_word[34])
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rd_len <= 10'h01 + { 6'h00, i_word[33:31] };
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rd_len <= 10'h01 + { 6'h00, r_word[33:31] };
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else
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else
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rd_len <= 10'h08 + { 1'b0, i_word[33:31], i_word[29:24] };
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rd_len <= 10'h08 + { 1'b0, r_word[33:31], r_word[29:24] };
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// Clock three, read the table value
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// Clock one, copy the input strobe, and input word
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// { o_stb, r_stb } = 4'h4 when done
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reg r_stb;
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// Maintaining ...
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reg [35:0] r_word;
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// r_word (clock 1)
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// r_addr, rd_len (clock 2)
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reg [31:0] cword;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_stb <= i_stb;
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cword <= compression_tbl[cmd_addr];
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// Pipeline the strobe signal to create an output strobe, 3 clocks later
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reg [2:0] r_stb;
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initial r_stb = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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r_word <= i_word;
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r_stb <= { r_stb[1:0], i_stb };
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// Clock two, now that the table value is valid, let's set our output
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// Clock four, now that the table value is valid, let's set our output
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// word.
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// word.
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// { o_stb, r_stb } = 4'h8 when done
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_stb <= r_stb;
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o_stb <= r_stb[2];
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// Maintaining ...
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// r_word (clock 1)
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// r_addr, rd_len (clock 2)
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// cword (clock 3)
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// Any/all of these can be pipelined for faster operation
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// However, speed is really limited by the speed of the I/O port. At
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// it's fastest, it's 1 bit per clock, 48 clocks per codeword therefore,
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// thus ... things will hold still for much longer than just 5 clocks.
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (r_word[35:30] == 6'b101110)
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if (r_word[35:30] == 6'b101110)
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o_word <= r_word;
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o_word <= r_word;
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else casez(r_word[35:30])
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else casez(r_word[35:30])
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6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
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6'b001??0: o_word <= { 4'h0, w_addr[31:0] };
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