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https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk
[/] [xulalx25soc/] [trunk/] [xula.ucf] - Diff between revs 117 and 118
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| Rev 117 |
Rev 118 |
| Line 138... |
Line 138... |
##############################
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##############################
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# Clock Nets
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# Clock Nets
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##############################
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##############################
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NET "i_clk_12mhz" TNM_NET = "i_clk_12mhz";
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NET "i_clk_12mhz" TNM_NET = "i_clk_12mhz";
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NET "i_ram_feedback_clk" TNM_NET = "i_ram_feedback_clk";
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NET "i_ram_feedback_clk" TNM_NET = "i_ram_feedback_clk";
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TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.0 ns HIGH 50%;
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#
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# TimeSpec. The source clock to the XuLA2-LX25 and LX9 boards is a 12MHz
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# crystal oscillator. 12MHz corresponds to an 83.3333ns clocks---which would
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# be the line below:
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#
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# (Please leave this commented ... I'll explain ...)
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# TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
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# TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.333333 ns HIGH 50%;
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# TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 10.0 ns HIGH 50%;
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#
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# However, ISE struggles to meet timing with this design. By slightly
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# adjusting the input clock speed faster in the hundreds of picoseconds range,
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# I can create timing closure. At one time, someone explained to me that I was
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# really just forcing the XISE to use a different random seed for starting.
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# This may well be the case, but ... it's worked for me so far.
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TIMESPEC "TSi_clk_12mhz" = PERIOD "i_clk_12mhz" 83.1 ns HIGH 50%;
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#
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# The following line is included for completeness. It is not used.
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TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 11.3 ns HIGH 50%;
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TIMESPEC "TSi_ram_feedback_clk" = PERIOD "i_ram_feedback_clk" 11.3 ns HIGH 50%;
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