| Line 1... |
Line 1... |
/*******************************************************************************************/
|
/*******************************************************************************************/
|
/** **/
|
/** **/
|
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
|
/** ORIGINAL COPYRIGHT (C) 2011, SYSTEMYDE INTERNATIONAL CORPORATION, ALL RIGHTS RESERVED **/
|
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
|
/** COPYRIGHT (C) 2012, SERGEY BELYASHOV **/
|
/** **/
|
/** **/
|
/** control module Rev 0.0 06/13/2012 **/
|
/** control module Rev 0.0 06/18/2012 **/
|
/** **/
|
/** **/
|
/*******************************************************************************************/
|
/*******************************************************************************************/
|
module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
|
module control (add_sel, alua_sel, alub_sel, aluop_sel, cflg_en, di_ctl, do_ctl, ex_af_pls,
|
ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst,
|
ex_bank_pls, ex_dehl_inst, halt_nxt, hflg_ctl, ief_ctl, if_frst, inta_frst,
|
imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh,
|
imd_ctl, ld_dmaa, ld_inst, ld_inta, ld_page, ld_wait, nflg_ctl, output_inh,
|
| Line 472... |
Line 472... |
endcase
|
endcase
|
end
|
end
|
`IF2B: state_nxt = `sDEC2;
|
`IF2B: state_nxt = `sDEC2;
|
`DEC2: begin
|
`DEC2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b001000110110,
|
|
12'b001000000110,
|
12'b001000000110,
|
12'b001000001110,
|
12'b001000001110,
|
12'b001000010110,
|
12'b001000010110,
|
12'b001000011110,
|
12'b001000011110,
|
12'b001000100110,
|
12'b001000100110,
|
12'b001000101110,
|
12'b001000101110,
|
|
12'b001000110110,
|
12'b001000111110,
|
12'b001000111110,
|
12'b001001xxx110,
|
12'b001001xxx110,
|
12'b001010xxx110,
|
12'b001010xxx110,
|
12'b001011xxx110,
|
12'b001011xxx110,
|
12'b010011100001,
|
12'b010011100001,
|
| Line 490... |
Line 490... |
12'b010011100101,
|
12'b010011100101,
|
12'b010111100001,
|
12'b010111100001,
|
12'b010111100011,
|
12'b010111100011,
|
12'b010111100101,
|
12'b010111100101,
|
12'b1xxx00110100,
|
12'b1xxx00110100,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00111110,
|
|
12'b1xxx00111111,
|
|
12'b1xxx00xx0111,
|
|
12'b1xxx00xx1111,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111,
|
12'b1xxx01101111,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx001,
|
12'b1xxx01xxx001,
|
|
12'b1xxx10000010,
|
12'b1xxx10000011,
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
12'b1xxx10001011,
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
12'b1xxx10010011,
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
12'b1xxx10011011,
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: state_nxt = `sADR2;
|
12'b1xxx10111011,
|
12'b010010001100,
|
12'b1xxx10111100,
|
12'b010010001101,
|
12'b1xxx11000010,
|
12'b010110001100,
|
12'b1xxx11000011,
|
12'b010110001101,
|
12'b1xxx11001010,
|
12'b010010000100,
|
12'b1xxx11001011: state_nxt = `sADR2;
|
12'b010010000101,
|
|
12'b010110000100,
|
|
12'b010110000101,
|
|
12'b010010100100,
|
|
12'b010010100101,
|
|
12'b010110100100,
|
|
12'b010110100101,
|
|
12'b010010111100,
|
|
12'b010010111101,
|
|
12'b010110111100,
|
|
12'b010110111101,
|
|
12'b010000100101,
|
|
12'b010000101101,
|
|
12'b010100100101,
|
|
12'b010100101101,
|
|
12'b010000100100,
|
|
12'b010000101100,
|
|
12'b010100100100,
|
|
12'b010100101100,
|
|
12'b0100011000xx,12'b01000110010x,12'b010001100111,
|
|
12'b0100011010xx,12'b01000110110x,12'b010001101111,
|
|
12'b0101011000xx,12'b01010110010x,12'b010101100111,
|
|
12'b0101011010xx,12'b01010110110x,12'b010101101111,
|
|
12'b0100010xx100,12'b01000110x100,12'b010001111100,
|
|
12'b0100010xx101,12'b01000110x101,12'b010001111101,
|
|
12'b0101010xx100,12'b01010110x100,12'b010101111100,
|
|
12'b0101010xx101,12'b01010110x101,12'b010101111101,
|
|
12'b010010110100,
|
|
12'b010010110101,
|
|
12'b010110110100,
|
|
12'b010110110101,
|
|
12'b010010011100,
|
|
12'b010010011101,
|
|
12'b010110011100,
|
|
12'b010110011101,
|
|
12'b010010010100,
|
|
12'b010010010101,
|
|
12'b010110010100,
|
|
12'b010110010101,
|
|
12'b010010101100,
|
|
12'b010010101101,
|
|
12'b010110101100,
|
|
12'b010110101101,
|
|
12'b001000110xxx,
|
|
12'b001000000xxx,
|
12'b001000000xxx,
|
12'b001000001xxx,
|
12'b001000001xxx,
|
12'b001000010xxx,
|
12'b001000010xxx,
|
12'b001000011xxx,
|
12'b001000011xxx,
|
12'b001000100xxx,
|
12'b001000100xxx,
|
12'b001000101xxx,
|
12'b001000101xxx,
|
|
12'b001000110xxx,
|
12'b001000111xxx,
|
12'b001000111xxx,
|
12'b001001xxxxxx,
|
12'b001001xxxxxx,
|
12'b001010xxxxxx,
|
12'b001010xxxxxx,
|
12'b001011xxxxxx,
|
12'b001011xxxxxx,
|
12'b010000100011,
|
12'b010000100011,
|
|
12'b010000100100,
|
|
12'b010000100101,
|
12'b010000101011,
|
12'b010000101011,
|
|
12'b010000101100,
|
|
12'b010000101101,
|
12'b010000xx1001,
|
12'b010000xx1001,
|
|
12'b01000110x0xx,12'b01000110x10x,12'b01000110x111,
|
|
12'b0100010xx10x,12'b01000110x10x,12'b01000111110x,
|
|
12'b010010000100,
|
|
12'b010010000101,
|
|
12'b010010001100,
|
|
12'b010010001101,
|
|
12'b010010010100,
|
|
12'b010010010101,
|
|
12'b010010011100,
|
|
12'b010010011101,
|
|
12'b010010100100,
|
|
12'b010010100101,
|
|
12'b010010101100,
|
|
12'b010010101101,
|
|
12'b010010110100,
|
|
12'b010010110101,
|
|
12'b010010111100,
|
|
12'b010010111101,
|
12'b010011111001,
|
12'b010011111001,
|
12'b010100100011,
|
12'b010100100011,
|
|
12'b010100100100,
|
|
12'b010100100101,
|
12'b010100101011,
|
12'b010100101011,
|
|
12'b010100101100,
|
|
12'b010100101101,
|
12'b010100xx1001,
|
12'b010100xx1001,
|
|
12'b01010110x0xx,12'b01010110x10x,12'b01010110x111,
|
|
12'b0101010xx10x,12'b01010110x10x,12'b01010111110x,
|
|
12'b010110000100,
|
|
12'b010110000101,
|
|
12'b010110001100,
|
|
12'b010110001101,
|
|
12'b010110010100,
|
|
12'b010110010101,
|
|
12'b010110011100,
|
|
12'b010110011101,
|
|
12'b010110100100,
|
|
12'b010110100101,
|
|
12'b010110101100,
|
|
12'b010110101101,
|
|
12'b010110110100,
|
|
12'b010110110101,
|
|
12'b010110111100,
|
|
12'b010110111101,
|
12'b010111111001,
|
12'b010111111001,
|
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
|
12'b1xxx00xxx100,
|
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01000110,
|
12'b1xxx01000110,
|
12'b1xxx01000111,
|
12'b1xxx01000111,
|
12'b1xxx01001111,
|
12'b1xxx01001111,
|
12'b1xxx01010110,
|
12'b1xxx01010110,
|
12'b1xxx01010111,
|
12'b1xxx01010111,
|
12'b1xxx01011110,
|
12'b1xxx01011110,
|
12'b1xxx01011111,
|
12'b1xxx01011111,
|
|
12'b1xxx01xx1100,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx1010,
|
12'b1xxx01xx1010: state_nxt = `sIF1B;
|
12'b1xxx01xx1100: state_nxt = `sIF1B;
|
|
12'b010011101001,
|
12'b010011101001,
|
12'b010111101001,
|
12'b010111101001,
|
12'b1xxx01110110: state_nxt = `sPCO;
|
12'b1xxx01110110: state_nxt = `sPCO;
|
default: state_nxt = `sOF1B;
|
default: state_nxt = `sOF1B;
|
endcase
|
endcase
|
end
|
end
|
`OF1B: begin
|
`OF1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011010011,
|
|
12'b000011011011,
|
|
12'b010000110100,
|
|
12'b010000110101,
|
|
12'b010001110xxx,
|
|
12'b010001xxx110,
|
|
12'b010010000110,
|
|
12'b010010001110,
|
|
12'b010010010110,
|
|
12'b010010011110,
|
|
12'b010010100110,
|
|
12'b010010101110,
|
|
12'b010010110110,
|
|
12'b010010111110,
|
|
12'b010100110100,
|
|
12'b010100110101,
|
|
12'b010101110xxx,
|
|
12'b010101xxx110,
|
|
12'b010110000110,
|
|
12'b010110001110,
|
|
12'b010110010110,
|
|
12'b010110011110,
|
|
12'b010110100110,
|
|
12'b010110101110,
|
|
12'b010110110110,
|
|
12'b010110111110,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx001,
|
|
12'b1xxx01110100: state_nxt = `sADR1;
|
|
12'b010000100110,
|
|
12'b010000101110,
|
|
12'b010100100110,
|
|
12'b010100101110,
|
|
12'b0000000xx110,12'b00000010x110,12'b000000111110,
|
12'b0000000xx110,12'b00000010x110,12'b000000111110,
|
12'b000011000110,
|
12'b000011000110,
|
12'b000011001110,
|
12'b000011001110,
|
12'b000011010110,
|
12'b000011010110,
|
12'b000011011110,
|
12'b000011011110,
|
12'b000011100110,
|
12'b000011100110,
|
12'b000011101110,
|
12'b000011101110,
|
12'b000011110110,
|
12'b000011110110,
|
12'b000011111110,
|
12'b000011111110,
|
|
12'b010000100110,
|
|
12'b010000101110,
|
|
12'b010100100110,
|
|
12'b010100101110,
|
|
12'b1xxx00110010,
|
|
12'b1xxx00110011,
|
|
12'b1xxx00xx0010,
|
|
12'b1xxx00xx0011,
|
|
12'b1xxx01010100,
|
|
12'b1xxx01010101,
|
12'b1xxx01100100: state_nxt = `sIF1A;
|
12'b1xxx01100100: state_nxt = `sIF1A;
|
12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
|
12'b000000100000: state_nxt = ( !zero_bit) ? `sPCA : `sIF1A;
|
12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
|
12'b000000101000: state_nxt = ( zero_bit) ? `sPCA : `sIF1A;
|
12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
|
12'b000000110000: state_nxt = (!carry_bit) ? `sPCA : `sIF1A;
|
12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
|
12'b000000111000: state_nxt = ( carry_bit) ? `sPCA : `sIF1A;
|
|
12'b011xxxxxxxxx: state_nxt = `sIF3A; //DD/FD + CB
|
12'b000000100010,
|
12'b000000100010,
|
12'b000000101010,
|
12'b000000101010,
|
12'b000000110010,
|
12'b000000110010,
|
12'b000000111010,
|
12'b000000111010,
|
12'b000000xx0001,
|
12'b000000xx0001,
|
| Line 672... |
Line 668... |
12'b1xxx01xx0011,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx1011: state_nxt = `sOF2A;
|
12'b1xxx01xx1011: state_nxt = `sOF2A;
|
12'b000000010000,
|
12'b000000010000,
|
12'b000000011000: state_nxt = `sPCA;
|
12'b000000011000: state_nxt = `sPCA;
|
12'b000000110110: state_nxt = `sWR2A;
|
12'b000000110110: state_nxt = `sWR2A;
|
default: state_nxt = `sIF3A;
|
default: state_nxt = `sADR1;
|
endcase
|
endcase
|
end
|
end
|
`OF2A: state_nxt = `sOF2B;
|
`OF2A: state_nxt = `sOF2B;
|
`OF2B: begin
|
`OF2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
| Line 716... |
Line 712... |
12'b000011100011,
|
12'b000011100011,
|
12'b000011xxx000,
|
12'b000011xxx000,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010000101010,
|
12'b010000101010,
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
12'b010011100001,
|
12'b010011100001,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010100101010,
|
12'b010100101010,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
12'b010111100001,
|
12'b010111100001,
|
12'b010111100011,
|
12'b010111100011,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
12'b1xxx01xx1011,
|
12'b1xxx01xx1011,
|
12'b1xxx100xx011,
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: state_nxt = `sRD1A;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: state_nxt = `sRD1A;
|
12'b000000100010,
|
12'b000000100010,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b010000100010,
|
12'b010000100010,
|
|
12'b010000111110,
|
|
12'b010000111111,
|
|
12'b010000xx1111,
|
12'b010011100101,
|
12'b010011100101,
|
12'b010100100010,
|
12'b010100100010,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx1111,
|
12'b010111100101,
|
12'b010111100101,
|
|
12'b1xxx00111110,
|
|
12'b1xxx00111111,
|
|
12'b1xxx00xx1111,
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110,
|
12'b1xxx01xx0011: state_nxt = `sWR1A;
|
12'b1xxx01xx0011: state_nxt = `sWR1A;
|
12'b000000000010,
|
12'b000000000010,
|
12'b000000010010,
|
12'b000000010010,
|
12'b000000110010,
|
12'b000000110010,
|
12'b000001110xxx,
|
12'b000001110xxx,
|
| Line 768... |
Line 803... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: state_nxt = `sBLK1;
|
12'b1xxx10111001: state_nxt = `sBLK1;
|
12'b1xxx100xx011,
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: state_nxt = `sWR1A;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: state_nxt = `sWR1A;
|
default: state_nxt = `sRD2A;
|
default: state_nxt = `sRD2A;
|
endcase
|
endcase
|
end
|
end
|
`RD2A: state_nxt = `sRD2B;
|
`RD2A: state_nxt = `sRD2B;
|
`RD2B: begin
|
`RD2B: begin
|
| Line 815... |
Line 869... |
12'b000011011011,
|
12'b000011011011,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b001001xxx110,
|
12'b001001xxx110,
|
12'b001001xxxxxx,
|
12'b001001xxxxxx,
|
12'b010000101010,
|
12'b010000101010,
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
12'b010001xxx110,
|
12'b010001xxx110,
|
12'b010010000110,
|
12'b010010000110,
|
12'b010010001110,
|
12'b010010001110,
|
12'b010010010110,
|
12'b010010010110,
|
12'b010010011110,
|
12'b010010011110,
|
| Line 826... |
Line 883... |
12'b010010101110,
|
12'b010010101110,
|
12'b010010110110,
|
12'b010010110110,
|
12'b010010111110,
|
12'b010010111110,
|
12'b010011100001,
|
12'b010011100001,
|
12'b010100101010,
|
12'b010100101010,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
12'b010101xxx110,
|
12'b010101xxx110,
|
12'b010110000110,
|
12'b010110000110,
|
12'b010110001110,
|
12'b010110001110,
|
12'b010110010110,
|
12'b010110010110,
|
12'b010110011110,
|
12'b010110011110,
|
| Line 838... |
Line 898... |
12'b010110110110,
|
12'b010110110110,
|
12'b010110111110,
|
12'b010110111110,
|
12'b010111100001,
|
12'b010111100001,
|
12'b011001xxx110,
|
12'b011001xxx110,
|
12'b011101xxx110,
|
12'b011101xxx110,
|
|
12'b1xxx00110100,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
12'b1xxx00xxx000,
|
12'b1xxx00xxx000,
|
12'b1xxx0x110100,
|
12'b1xxx00xxx100,
|
|
12'b1xxx01110100,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xx1011: state_nxt = `sIF1A;
|
12'b1xxx01xx1011: state_nxt = `sIF1A;
|
12'b000011001001,
|
12'b000011001001,
|
12'b000011xxx000,
|
12'b000011xxx000,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
| Line 856... |
Line 921... |
endcase
|
endcase
|
end
|
end
|
`WR1A: state_nxt = `sWR1B;
|
`WR1A: state_nxt = `sWR1B;
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx1000x011,
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011: state_nxt = `sIF1A;
|
12'b1xxx10101011,
|
12'b1xxx1001x011,
|
12'b1xxx10101100: state_nxt = `sIF1A;
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010,
|
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111000,
|
|
12'b1xxx10111010,
|
12'b1xxx10111011,
|
12'b1xxx10111011,
|
12'b1xxx10110000,
|
12'b1xxx10111100,
|
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
default: state_nxt = `sWR2A;
|
default: state_nxt = `sWR2A;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: state_nxt = `sWR2B;
|
`WR2A: state_nxt = `sWR2B;
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx1001x011,
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10100000,
|
|
12'b1xxx10100010,
|
|
12'b1xxx10100011,
|
|
12'b1xxx10101000,
|
|
12'b1xxx10101010,
|
|
12'b1xxx10101011,
|
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010,
|
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111000,
|
|
12'b1xxx10111010,
|
12'b1xxx10111011,
|
12'b1xxx10111011,
|
12'b1xxx10110000,
|
12'b1xxx10111100,
|
12'b1xxx10111000: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: state_nxt = (tflg_reg || intr_reg || dmar_reg) ? `sPCA : `sRD2A;
|
default: state_nxt = `sIF1A;
|
default: state_nxt = `sIF1A;
|
endcase
|
endcase
|
end
|
end
|
`BLK1: state_nxt = `sBLK2;
|
`BLK1: state_nxt = `sBLK2;
|
`BLK2: begin
|
`BLK2: begin
|
| Line 897... |
Line 997... |
endcase
|
endcase
|
end
|
end
|
`PCA: state_nxt = `sPCO;
|
`PCA: state_nxt = `sPCO;
|
`PCO: begin
|
`PCO: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000001110110: state_nxt = `sHLTA;
|
12'b000001110110,
|
12'b1xxx01110110: state_nxt = `sHLTA;
|
12'b1xxx01110110: state_nxt = `sHLTA;
|
default: state_nxt = `sIF1A;
|
default: state_nxt = `sIF1A;
|
endcase
|
endcase
|
end
|
end
|
`HLTA: state_nxt = `sHLTB;
|
`HLTA: state_nxt = `sHLTB;
|
| Line 930... |
Line 1030... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000010000,
|
12'b000000010000,
|
12'b000000011000,
|
12'b000000011000,
|
12'b000011010011,
|
12'b000011010011,
|
12'b000011011011,
|
12'b000011011011,
|
12'b010x00110100,
|
12'b010000110001,
|
12'b010x00110101,
|
12'b010000110100,
|
12'b010x011100xx,
|
12'b010000110101,
|
12'b010x0111010x,
|
12'b010000110111,
|
12'b010x01110111,
|
12'b010000111110,
|
12'b010x010xx110,
|
12'b010000111111,
|
12'b010x0110x110,
|
12'b010000xx0111,
|
12'b010x01111110,
|
12'b010000xx1111,
|
12'b010x10000110,
|
12'b010001110xxx,
|
12'b010x10001110,
|
12'b010001xxx110,
|
12'b010x10010110,
|
12'b010010000110,
|
12'b010x10011110,
|
12'b010010001110,
|
12'b010x10100110,
|
12'b010010010110,
|
12'b010x10101110,
|
12'b010010011110,
|
12'b010x10110110,
|
12'b010010100110,
|
12'b010x10111110: tran_sel = `TRAN_IDL;
|
12'b010010101110,
|
|
12'b010010110110,
|
|
12'b010010111110,
|
|
12'b010100110001,
|
|
12'b010100110100,
|
|
12'b010100110101,
|
|
12'b010100110111,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx0111,
|
|
12'b010100xx1111,
|
|
12'b010101110xxx,
|
|
12'b010101xxx110,
|
|
12'b010110000110,
|
|
12'b010110001110,
|
|
12'b010110010110,
|
|
12'b010110011110,
|
|
12'b010110100110,
|
|
12'b010110101110,
|
|
12'b010110110110,
|
|
12'b010110111110,
|
|
12'b1xxx00110010,
|
|
12'b1xxx00110011,
|
|
12'b1xxx00xx0010,
|
|
12'b1xxx00xx0011,
|
|
12'b1xxx01010100,
|
|
12'b1xxx01010101,
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: tran_sel = `TRAN_IDL;
|
12'b000000100000: tran_sel = ( zero_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000100000: tran_sel = ( zero_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000101000: tran_sel = ( !zero_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000101000: tran_sel = ( !zero_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000110000: tran_sel = ( carry_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000110000: tran_sel = ( carry_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000111000: tran_sel = (!carry_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000111000: tran_sel = (!carry_bit) ? `TRAN_IF : `TRAN_IDL;
|
12'b000000110110: tran_sel = `TRAN_MEM;
|
12'b000000110110: tran_sel = `TRAN_MEM;
|
| Line 988... |
Line 1116... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011010011,
|
12'b000011010011,
|
12'b000011011011,
|
12'b000011011011,
|
12'b1xxx00xxx000,
|
12'b1xxx00xxx000,
|
12'b1xxx00xxx001,
|
12'b1xxx00xxx001,
|
|
12'b1xxx01110100,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx001,
|
12'b1xxx01xxx001,
|
12'b1xxx01110100,
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: tran_sel = `TRAN_IO;
|
12'b1xxx10111010,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: tran_sel = `TRAN_IO;
|
12'b000011001001,
|
12'b000011001001,
|
12'b000011xxx000,
|
12'b000011xxx000,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b010011100001,
|
12'b010011100001,
|
12'b010011100101,
|
12'b010011100101,
|
12'b010111100001,
|
12'b010111100001,
|
12'b010111100101,
|
12'b010111100101,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101: tran_sel = `TRAN_STK;
|
12'b1xxx01001101,
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: tran_sel = `TRAN_STK;
|
default: tran_sel = `TRAN_MEM;
|
default: tran_sel = `TRAN_MEM;
|
endcase
|
endcase
|
end
|
end
|
`RD1B: begin
|
`RD1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: tran_sel = `TRAN_IDL;
|
12'b1xxx10111001: tran_sel = `TRAN_IDL;
|
12'b1xxx100xx011,
|
12'b1xxx10000011,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
12'b1xxx10110100,
|
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011: tran_sel = `TRAN_IO;
|
12'b000011001001,
|
12'b000011001001,
|
12'b000011xxx000,
|
12'b000011xxx000,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b010011100001,
|
12'b010011100001,
|
12'b010111100001,
|
12'b010111100001,
|
| Line 1057... |
Line 1206... |
12'b000010111110,
|
12'b000010111110,
|
12'b000011011011,
|
12'b000011011011,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b001001xxx110,
|
12'b001001xxx110,
|
12'b010000101010,
|
12'b010000101010,
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
12'b010001xxx110,
|
12'b010001xxx110,
|
12'b010010000110,
|
12'b010010000110,
|
12'b010010001110,
|
12'b010010001110,
|
12'b010010010110,
|
12'b010010010110,
|
12'b010010011110,
|
12'b010010011110,
|
| Line 1068... |
Line 1220... |
12'b010010101110,
|
12'b010010101110,
|
12'b010010110110,
|
12'b010010110110,
|
12'b010010111110,
|
12'b010010111110,
|
12'b010011100001,
|
12'b010011100001,
|
12'b010100101010,
|
12'b010100101010,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
12'b010101xxx110,
|
12'b010101xxx110,
|
12'b010110000110,
|
12'b010110000110,
|
12'b010110001110,
|
12'b010110001110,
|
12'b010110010110,
|
12'b010110010110,
|
12'b010110011110,
|
12'b010110011110,
|
| Line 1080... |
Line 1235... |
12'b010110110110,
|
12'b010110110110,
|
12'b010110111110,
|
12'b010110111110,
|
12'b010111100001,
|
12'b010111100001,
|
12'b011001xxx110,
|
12'b011001xxx110,
|
12'b011101xxx110,
|
12'b011101xxx110,
|
12'b1xxx01110100,
|
12'b1xxx00110100,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
|
12'b1xxx00xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
|
12'b1xxx01xx1011: tran_sel = `TRAN_IF;
|
12'b1xxx100xx011,
|
12'b1xxx10000011,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = `TRAN_IO;
|
12'b1xxx10110100,
|
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011: tran_sel = `TRAN_IO;
|
12'b000011100011,
|
12'b000011100011,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010111100011: tran_sel = `TRAN_STK;
|
12'b010111100011: tran_sel = `TRAN_STK;
|
default: tran_sel = `TRAN_MEM;
|
default: tran_sel = `TRAN_MEM;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
12'b1xxx10111010,
|
12'b1xxx1001x011,
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000,
|
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
12'b1xxx10110100,
|
12'b1xxx10100000,
|
12'b1xxx10111000,
|
12'b1xxx10100010,
|
12'b1xxx10111011,
|
12'b1xxx10100011,
|
12'b1xxx10111100,
|
12'b1xxx10101000,
|
12'b1xxx11000011,
|
12'b1xxx10101010,
|
12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
12'b1xxx10101011: tran_sel = `TRAN_IF;
|
|
12'b000000100010,
|
12'b000000100010,
|
12'b010000100010,
|
12'b010000100010,
|
|
12'b010000111110,
|
|
12'b010000111111,
|
|
12'b010000xx1111,
|
12'b010100100010,
|
12'b010100100010,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx1111,
|
|
12'b1xxx00111110,
|
|
12'b1xxx00111111,
|
|
12'b1xxx00xx1111,
|
12'b1xxx01xx0011: tran_sel = `TRAN_MEM;
|
12'b1xxx01xx0011: tran_sel = `TRAN_MEM;
|
default: tran_sel = `TRAN_STK;
|
12'b000011001101,
|
|
12'b000011100011,
|
|
12'b000011xxx100,
|
|
12'b000011xxx111,
|
|
12'b000011xx0101,
|
|
12'b0001xxxxxxxx,
|
|
12'b010011100011,
|
|
12'b010011100101,
|
|
12'b010111100011,
|
|
12'b010111100101,
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: tran_sel = `TRAN_STK;
|
|
default: tran_sel = `TRAN_IF;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010,
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
12'b1xxx10111010: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_IO;
|
12'b1xxx1001x011,
|
12'b1xxx10010011,
|
|
12'b1xxx10011011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000,
|
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
12'b1xxx10110100,
|
|
12'b1xxx10111000,
|
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011: tran_sel = (tflg_reg || intr_reg || dmar_reg) ? `TRAN_IDL : `TRAN_MEM;
|
default: tran_sel = `TRAN_IF;
|
default: tran_sel = `TRAN_IF;
|
endcase
|
endcase
|
end
|
end
|
`BLK2: begin
|
`BLK2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
| Line 1277... |
Line 1482... |
12'b010011101001,
|
12'b010011101001,
|
12'b010111100101,
|
12'b010111100101,
|
12'b010111101001,
|
12'b010111101001,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx001,
|
12'b1xxx01xxx001,
|
12'b1xxx100xx011,
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
| Line 1290... |
Line 1502... |
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: add_sel = `ADD_ALU;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: add_sel = `ADD_ALU8;
|
12'b001000000110,
|
12'b001000000110,
|
12'b001000001110,
|
12'b001000001110,
|
12'b001000010110,
|
12'b001000010110,
|
12'b001000011110,
|
12'b001000011110,
|
12'b001000100110,
|
12'b001000100110,
|
| Line 1305... |
Line 1527... |
12'b001000110110,
|
12'b001000110110,
|
12'b001000111110,
|
12'b001000111110,
|
12'b001001xxx110,
|
12'b001001xxx110,
|
12'b001010xxx110,
|
12'b001010xxx110,
|
12'b001011xxx110,
|
12'b001011xxx110,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx00110100,
|
12'b1xxx00110100,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00111110,
|
|
12'b1xxx00111111,
|
|
12'b1xxx00xx0111,
|
|
12'b1xxx00xx1111,
|
12'b1xxx01100111,
|
12'b1xxx01100111,
|
12'b1xxx01101111: add_sel = `ADD_HL;
|
12'b1xxx01101111: add_sel = `ADD_HL;
|
12'b010011100001,
|
12'b010011100001,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010111100001,
|
12'b010111100001,
|
| Line 1358... |
Line 1588... |
12'b010000110101,
|
12'b010000110101,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010100110100,
|
12'b010100110100,
|
12'b010100110101,
|
12'b010100110101,
|
12'b010111100011,
|
12'b010111100011,
|
12'b011x00xxxxxx,
|
12'b011000000110,
|
12'b011x1xxxxxxx,
|
12'b011000001110,
|
|
12'b011000010110,
|
|
12'b011000011110,
|
|
12'b011000100110,
|
|
12'b011000101110,
|
|
12'b011000110110,
|
|
12'b011000111110,
|
|
12'b011010xxx110,
|
|
12'b011011xxx110,
|
|
12'b011100000110,
|
|
12'b011100001110,
|
|
12'b011100010110,
|
|
12'b011100011110,
|
|
12'b011100100110,
|
|
12'b011100101110,
|
|
12'b011100110110,
|
|
12'b011100111110,
|
|
12'b011110xxx110,
|
|
12'b011111xxx110,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
| Line 1372... |
Line 1626... |
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
12'b1xxx10111011,
|
//12'b1xxx01110100,
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: add_sel = `ADD_ALU;
|
12'b1xxx100xx011: add_sel = `ADD_ALU8;
|
12'b1xxx100xx011: add_sel = `ADD_ALU8;
|
12'b000000110100,
|
12'b000000110100,
|
12'b000000110101,
|
12'b000000110101,
|
12'b000000xxx100,
|
12'b000000xxx100,
|
12'b000000xxx101,
|
12'b000000xxx101,
|
| Line 1409... |
Line 1668... |
default: add_sel = `ADD_PC;
|
default: add_sel = `ADD_PC;
|
endcase
|
endcase
|
end
|
end
|
`WR1A: begin
|
`WR1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx1000x011,
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: add_sel = `ADD_ALU8;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011: add_sel = `ADD_PC;
|
12'b1xxx10101011,
|
|
12'b1xxx10101100: add_sel = `ADD_PC;
|
default: add_sel = `ADD_ALU;
|
default: add_sel = `ADD_ALU;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011001101,
|
12'b000011001101,
|
12'b000011xxx100,
|
12'b000011xxx100,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b1xxx100xx011,
|
12'b1xxx10000011,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: add_sel = `ADD_ALU;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: add_sel = `ADD_ALU;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: add_sel = `ADD_ALU8;
|
default: add_sel = `ADD_PC;
|
default: add_sel = `ADD_PC;
|
endcase
|
endcase
|
end
|
end
|
`BLK1: begin
|
`BLK1: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
| Line 1542... |
Line 1825... |
default: pc_sel = `PC_LD;
|
default: pc_sel = `PC_LD;
|
endcase
|
endcase
|
end
|
end
|
`DEC2: begin
|
`DEC2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b010000100110,
|
12'b001000000110,
|
12'b010000101110,
|
12'b001000001110,
|
12'b010100100110,
|
12'b001000010110,
|
12'b010100101110,
|
12'b001000011110,
|
12'b010011001011, //DD+CB prefix
|
12'b001000100110,
|
12'b010111001011, //FD+CB prefix
|
12'b001000101110,
|
12'b010000100001,
|
12'b001000110110,
|
12'b010000100010,
|
12'b001000111110,
|
12'b010000101010,
|
12'b001001xxx110,
|
12'b010000110100,
|
12'b001010xxx110,
|
12'b010000110101,
|
12'b001011xxx110,
|
12'b010000110110,
|
12'b010011100001,
|
12'b010001110xxx,
|
12'b010011100011,
|
12'b010001xxx110,
|
12'b010011100101,
|
12'b010010000110,
|
12'b010111100001,
|
12'b010010001110,
|
12'b010111100011,
|
12'b010010010110,
|
12'b010111100101,
|
12'b010010011110,
|
12'b1xxx00110100,
|
12'b010010100110,
|
12'b1xxx00110110,
|
12'b010010101110,
|
12'b1xxx00110111,
|
12'b010010110110,
|
12'b1xxx00111110,
|
12'b010010111110,
|
12'b1xxx00111111,
|
12'b010011101001,
|
12'b1xxx00xx0111,
|
12'b010100100001,
|
12'b1xxx00xx1111,
|
12'b010100100010,
|
12'b1xxx01100111,
|
12'b010100101010,
|
12'b1xxx01101111,
|
12'b010100110100,
|
12'b1xxx01110110,
|
12'b010100110101,
|
12'b1xxx01xxx000,
|
12'b010100110110,
|
12'b1xxx01xxx001,
|
12'b010101110xxx,
|
12'b1xxx10000010,
|
12'b010101xxx110,
|
12'b1xxx10000011,
|
12'b010110000110,
|
12'b1xxx10000100,
|
12'b010110001110,
|
12'b1xxx10001010,
|
12'b010110010110,
|
12'b1xxx10001011,
|
12'b010110011110,
|
12'b1xxx10001100,
|
12'b010110100110,
|
12'b1xxx10010010,
|
12'b010110101110,
|
12'b1xxx10010011,
|
12'b010110110110,
|
12'b1xxx10010100,
|
12'b010110111110,
|
12'b1xxx10011010,
|
12'b010111101001,
|
12'b1xxx10011011,
|
12'b1xxx00xxx000,
|
12'b1xxx10011100,
|
12'b1xxx00xxx001,
|
12'b1xxx10100000,
|
12'b1xxx01100100,
|
12'b1xxx10100001,
|
12'b1xxx01110100,
|
12'b1xxx10100010,
|
12'b1xxx01000101,
|
12'b1xxx10100011,
|
12'b1xxx01001101,
|
12'b1xxx10100100,
|
12'b1xxx01xx0011,
|
12'b1xxx10101000,
|
12'b1xxx01xx1011: pc_sel = `PC_LD;
|
12'b1xxx10101001,
|
12'b010010001100,
|
12'b1xxx10101010,
|
12'b010010001101,
|
12'b1xxx10101011,
|
12'b010110001100,
|
12'b1xxx10101100,
|
12'b010110001101,
|
|
12'b010010000100,
|
|
12'b010010000101,
|
|
12'b010110000100,
|
|
12'b010110000101,
|
|
12'b010010100100,
|
|
12'b010010100101,
|
|
12'b010110100100,
|
|
12'b010110100101,
|
|
12'b010010111100,
|
|
12'b010010111101,
|
|
12'b010110111100,
|
|
12'b010110111101,
|
|
12'b010000100101,
|
|
12'b010000101101,
|
|
12'b010100100101,
|
|
12'b010100101101,
|
|
12'b010000100100,
|
|
12'b010000101100,
|
|
12'b010100100100,
|
|
12'b010100101100,
|
|
12'b0100011000xx,12'b01000110010x,12'b010001100111,
|
|
12'b0100011010xx,12'b01000110110x,12'b010001101111,
|
|
12'b0101011000xx,12'b01010110010x,12'b010101100111,
|
|
12'b0101011010xx,12'b01010110110x,12'b010101101111,
|
|
12'b0100010xx100,12'b01000110x100,12'b010001111100,
|
|
12'b0100010xx101,12'b01000110x101,12'b010001111101,
|
|
12'b0101010xx100,12'b01010110x100,12'b010101111100,
|
|
12'b0101010xx101,12'b01010110x101,12'b010101111101,
|
|
12'b010010110100,
|
|
12'b010010110101,
|
|
12'b010110110100,
|
|
12'b010110110101,
|
|
12'b010010011100,
|
|
12'b010010011101,
|
|
12'b010110011100,
|
|
12'b010110011101,
|
|
12'b010010010100,
|
|
12'b010010010101,
|
|
12'b010110010100,
|
|
12'b010110010101,
|
|
12'b010010101100,
|
|
12'b010010101101,
|
|
12'b010110101100,
|
|
12'b010110101101,
|
|
12'b0010000000xx,12'b00100000010x,12'b001000000111,
|
|
12'b0010000010xx,12'b00100000110x,12'b001000001111,
|
|
12'b0010000100xx,12'b00100001010x,12'b001000010111,
|
|
12'b0010000110xx,12'b00100001110x,12'b001000011111,
|
|
12'b0010001000xx,12'b00100010010x,12'b001000100111,
|
|
12'b0010001010xx,12'b00100010110x,12'b001000101111,
|
|
12'b0010001100xx,12'b00100011010x,12'b001000110111,
|
|
12'b0010001110xx,12'b00100011110x,12'b001000111111,
|
|
12'b001001xxx0xx,12'b001001xxx10x,12'b001001xxx111,
|
|
12'b001010xxx0xx,12'b001010xxx10x,12'b001010xxx111,
|
|
12'b001011xxx0xx,12'b001011xxx10x,12'b001011xxx111,
|
|
12'b010000100011,
|
|
12'b010000101011,
|
|
12'b010000xx1001,
|
|
12'b010011111001,
|
|
12'b010100100011,
|
|
12'b010100101011,
|
|
12'b010100xx1001,
|
|
12'b010111111001,
|
|
12'b1xxx000xx100,12'b1xxx0010x100,12'b1xxx00111100,
|
|
12'b1xxx01xx1100,
|
|
12'b1xxx01000100,
|
|
12'b1xxx01000110,
|
|
12'b1xxx01000111,
|
|
12'b1xxx01001111,
|
|
12'b1xxx01010110,
|
|
12'b1xxx01010111,
|
|
12'b1xxx01011110,
|
|
12'b1xxx01011111,
|
|
12'b1xxx01xx0010,
|
|
12'b1xxx01xx1010: pc_sel = `PC_NILD;
|
|
default: pc_sel = `PC_NUL;
|
|
endcase
|
|
end
|
|
`OF2A: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b000000100010,
|
|
12'b000000101010,
|
|
12'b000000110010,
|
|
12'b000000111010,
|
|
12'b000000xx0001,
|
|
12'b000011000011,
|
|
12'b000011001101,
|
|
12'b000011xxx010,
|
|
12'b000011xxx100,
|
|
12'b010000100001,
|
|
12'b010000100010,
|
|
12'b010000101010,
|
|
12'b010000110110,
|
|
12'b010100100001,
|
|
12'b010100100010,
|
|
12'b010100101010,
|
|
12'b010100110110,
|
|
12'b1xxx01xx0011,
|
|
12'b1xxx01xx1011: pc_sel = `PC_LD;
|
|
default: pc_sel = `PC_NUL;
|
|
endcase
|
|
end
|
|
`IF3A: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b01xx11001011: pc_sel = `PC_LD;
|
|
default: pc_sel = `PC_NUL;
|
|
endcase
|
|
end
|
|
`RD1B,
|
|
`RD2B: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx1001x011,
|
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: pc_sel = `PC_INT;
|
12'b1xxx10111011,
|
default: pc_sel = `PC_NUL;
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: pc_sel = `PC_NUL;
|
|
12'b010000100001,
|
|
12'b010000100010,
|
|
12'b010000100110,
|
|
12'b010000101010,
|
|
12'b010000101110,
|
|
12'b010000110001,
|
|
12'b010000110100,
|
|
12'b010000110101,
|
|
12'b010000110110,
|
|
12'b010000110111,
|
|
12'b010000111110,
|
|
12'b010000111111,
|
|
12'b010000xx0111,
|
|
12'b010000xx1111,
|
|
12'b010001110xxx,
|
|
12'b010001xxx110,
|
|
12'b010010000110,
|
|
12'b010010001110,
|
|
12'b010010010110,
|
|
12'b010010011110,
|
|
12'b010010100110,
|
|
12'b010010101110,
|
|
12'b010010110110,
|
|
12'b010010111110,
|
|
12'b010011101001,
|
|
12'b010100100001,
|
|
12'b010100100010,
|
|
12'b010100100110,
|
|
12'b010100101010,
|
|
12'b010100101110,
|
|
12'b010100110001,
|
|
12'b010100110100,
|
|
12'b010100110101,
|
|
12'b010100110110,
|
|
12'b010100110111,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx0111,
|
|
12'b010100xx1111,
|
|
12'b010101110xxx,
|
|
12'b010101xxx110,
|
|
12'b010110000110,
|
|
12'b010110001110,
|
|
12'b010110010110,
|
|
12'b010110011110,
|
|
12'b010110100110,
|
|
12'b010110101110,
|
|
12'b010110110110,
|
|
12'b010110111110,
|
|
12'b010111101001,
|
|
12'b010011001011, //DD+CB prefix
|
|
12'b010111001011, //FD+CB prefix
|
|
12'b1xxx00110010,
|
|
12'b1xxx00110011,
|
|
12'b1xxx00xx0010,
|
|
12'b1xxx00xx0011,
|
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx001,
|
|
12'b1xxx01000101,
|
|
12'b1xxx01001101,
|
|
12'b1xxx01010100,
|
|
12'b1xxx01010101,
|
|
12'b1xxx01100100,
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110,
|
|
12'b1xxx01110100,
|
|
12'b1xxx01xx1011,
|
|
12'b1xxx01xx0011: pc_sel = `PC_LD;
|
|
default: pc_sel = `PC_NILD;
|
endcase
|
endcase
|
end
|
end
|
|
`OF2A,
|
|
`IF3A: pc_sel = `PC_LD;
|
|
`RD1B,
|
|
`RD2B: pc_sel = `PC_INT;
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011001101,
|
12'b000011001101,
|
12'b000011xxx100,
|
12'b000011xxx100,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
| Line 1745... |
Line 1993... |
`PCO: begin
|
`PCO: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011101001,
|
12'b000011101001,
|
12'b010011101001,
|
12'b010011101001,
|
12'b010111101001,
|
12'b010111101001,
|
12'b1xxx1001x011,
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: pc_sel = `PC_LD;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: pc_sel = `PC_LD;
|
default: pc_sel = `PC_NUL;
|
default: pc_sel = `PC_NUL;
|
endcase
|
endcase
|
end
|
end
|
`IF1A: begin
|
`IF1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b0001xxxxxxxx,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101: pc_sel = `PC_LD;
|
12'b0001xxxxxxxx: pc_sel = `PC_LD;
|
12'b1xxx10010010,
|
12'b1xxx1001x011,
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: pc_sel = `PC_NILD2;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: pc_sel = `PC_NILD2;
|
default: pc_sel = `PC_NILD;
|
default: pc_sel = `PC_NILD;
|
endcase
|
endcase
|
end
|
end
|
`HLTA: pc_sel = `PC_INT;
|
`HLTA: pc_sel = `PC_INT;
|
`DMA1: pc_sel = `PC_DMA;
|
`DMA1: pc_sel = `PC_DMA;
|
| Line 1837... |
Line 2107... |
`RD1B: di_ctl = `DI_DI0;
|
`RD1B: di_ctl = `DI_DI0;
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000101010,
|
12'b000000101010,
|
12'b000011001001,
|
12'b000011001001,
|
12'b010x00101010,
|
|
12'b010x11100001,
|
|
12'b010x11100011,
|
|
12'b000011100011,
|
12'b000011100011,
|
12'b1xxx01000101,
|
|
12'b1xxx01001101,
|
|
12'b1xxx01xx1011,
|
|
12'b000011xxx000,
|
12'b000011xxx000,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b0001xxxxxxxx: di_ctl = `DI_DI1;
|
12'b0001xxxxxxxx,
|
|
12'b010000101010,
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
|
12'b010011100001,
|
|
12'b010011100011,
|
|
12'b010100101010,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
|
12'b010111100001,
|
|
12'b010111100011,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
|
12'b1xxx01000101,
|
|
12'b1xxx01001101,
|
|
12'b1xxx01xx1011: di_ctl = `DI_DI1;
|
default: di_ctl = `DI_DI0;
|
default: di_ctl = `DI_DI0;
|
endcase
|
endcase
|
end
|
end
|
`INTB: di_ctl = `DI_DI0;
|
`INTB: di_ctl = `DI_DI0;
|
default: di_ctl = `DI_NUL;
|
default: di_ctl = `DI_NUL;
|
| Line 1865... |
Line 2147... |
always @ (inst_reg or page_reg or state_reg) begin
|
always @ (inst_reg or page_reg or state_reg) begin
|
casex (state_reg) //synopsys parallel_case
|
casex (state_reg) //synopsys parallel_case
|
`WR1A: begin
|
`WR1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011001101,
|
12'b000011001101,
|
12'b010x11100101,
|
|
12'b000011xxx100,
|
12'b000011xxx100,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b0001xxxxxxxx: do_ctl = `DO_MSB;
|
12'b0001xxxxxxxx,
|
12'b1xxx100xx011,
|
12'b010011100101,
|
|
12'b010111100101,
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: do_ctl = `DO_MSB;
|
|
12'b1xxx10000011,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
12'b1xxx10110100,
|
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011: do_ctl = `DO_IO;
|
default: do_ctl = `DO_LSB;
|
default: do_ctl = `DO_LSB;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000100010,
|
12'b000000100010,
|
12'b010x00100010,
|
|
12'b010x11100011,
|
|
12'b000011100011,
|
12'b000011100011,
|
|
12'b010000100010,
|
|
12'b010000111110,
|
|
12'b010000111111,
|
|
12'b010000xx1111,
|
|
12'b010011100011,
|
|
12'b010100100010,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx1111,
|
|
12'b010111100011,
|
|
12'b1xxx00111110,
|
|
12'b1xxx00111111,
|
|
12'b1xxx00xx1111,
|
12'b1xxx01xx0011: do_ctl = `DO_MSB;
|
12'b1xxx01xx0011: do_ctl = `DO_MSB;
|
12'b000011010011,
|
12'b000011010011,
|
12'b1xxx0xxxx001,
|
12'b1xxx00xxx001,
|
12'b1xxx100xx011,
|
12'b1xxx01xxx001,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011011,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
12'b1xxx10111011: do_ctl = `DO_IO;
|
default: do_ctl = `DO_LSB;
|
default: do_ctl = `DO_LSB;
|
endcase
|
endcase
|
end
|
end
|
default: do_ctl = `DO_NUL;
|
default: do_ctl = `DO_NUL;
|
| Line 1941... |
Line 2254... |
end
|
end
|
`IF2B: aluop_sel = `ALUOP_ADD;
|
`IF2B: aluop_sel = `ALUOP_ADD;
|
`DEC2: begin
|
`DEC2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx01xx1010: aluop_sel = `ALUOP_ADC;
|
12'b1xxx01xx1010: aluop_sel = `ALUOP_ADC;
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b010000100011,
|
12'b010000100011,
|
12'b010000101011,
|
12'b010000101011,
|
12'b010000xx1001,
|
12'b010000xx1001,
|
12'b010011100101,
|
12'b010011100101,
|
12'b010100100011,
|
12'b010100100011,
|
| Line 2056... |
Line 2371... |
endcase
|
endcase
|
end
|
end
|
`IF3A: aluop_sel = `ALUOP_ADS;
|
`IF3A: aluop_sel = `ALUOP_ADS;
|
`ADR1: begin
|
`ADR1: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx00xxx00x,
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: aluop_sel = `ALUOP_ADD;
|
12'b000000100010,
|
12'b000000100010,
|
12'b000000101010,
|
12'b000000101010,
|
12'b000000110010,
|
12'b000000110010,
|
12'b000000111010,
|
12'b000000111010,
|
12'b000011010011,
|
12'b000011010011,
|
| Line 2068... |
Line 2384... |
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010000100010,
|
12'b010000100010,
|
12'b010000101010,
|
12'b010000101010,
|
12'b010100100010,
|
12'b010100100010,
|
12'b010100101010,
|
12'b010100101010,
|
12'b1xxx01100100,
|
12'b1xxx00xxx000,
|
|
12'b1xxx00xxx001,
|
12'b1xxx01110100,
|
12'b1xxx01110100,
|
12'b1xxx01xx0011,
|
12'b1xxx01xx1011,
|
12'b1xxx01xx1011: aluop_sel = `ALUOP_PASS;
|
12'b1xxx01xx0011: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_ADS;
|
default: aluop_sel = `ALUOP_ADS;
|
endcase
|
endcase
|
end
|
end
|
`ADR2: begin
|
`ADR2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111001,
|
12'b1xxx100xx011,
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: aluop_sel = `ALUOP_ADS;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111010: aluop_sel = `ALUOP_BADD;
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`RD1A: begin
|
`RD1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx100xx011,
|
12'b000000101010,
|
12'b1xxx10100000,
|
12'b000011001001,
|
|
12'b000011100011,
|
|
12'b000011xxx000,
|
|
12'b000011xx0001,
|
|
12'b0001xxxxxxxx,
|
|
12'b010000101010,
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
|
12'b010011100001,
|
|
12'b010011100011,
|
|
12'b010100101010,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
|
12'b010111100001,
|
|
12'b010111100011,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
|
12'b1xxx01000101,
|
|
12'b1xxx01001101,
|
|
12'b1xxx01xx1011: aluop_sel = `ALUOP_ADD;
|
|
default: aluop_sel = `ALUOP_PASS;
|
|
endcase
|
|
end
|
|
`RD1B: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: aluop_sel = `ALUOP_PASS;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
default: aluop_sel = `ALUOP_ADD;
|
|
endcase
|
|
end
|
|
`RD1B: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
12'b1xxx100xx011,
|
default: aluop_sel = `ALUOP_PASS;
|
12'b1xxx10100000,
|
|
12'b1xxx10101000,
|
|
12'b1xxx10110000,
|
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
|
default: aluop_sel = `ALUOP_BAND;
|
|
endcase
|
endcase
|
end
|
end
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011001001,
|
12'b000011001001,
|
| Line 2139... |
Line 2491... |
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010011100001,
|
12'b010011100001,
|
12'b010111100001,
|
12'b010111100001,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
|
12'b1xxx10101100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111010,
|
12'b1xxx100xx011: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: aluop_sel = `ALUOP_ADD;
|
|
12'b1xxx10000011,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10011011: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b000000110100,
|
12'b000000xxx100,
|
12'b000000xxx100,
|
12'b010000110100,
|
12'b010000110100,
|
12'b010100110100: aluop_sel = `ALUOP_BADD;
|
12'b010100110100: aluop_sel = `ALUOP_BADD;
|
12'b0x1x10xxxxxx,
|
12'b001010xxx110,
|
|
12'b001010xxxxxx,
|
|
12'b011010xxx110,
|
|
12'b011110xxx110,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BAND;
|
|
12'b000000110101,
|
12'b000000xxx101,
|
12'b000000xxx101,
|
12'b010000110101,
|
12'b010000110101,
|
12'b010100110101: aluop_sel = `ALUOP_BDEC;
|
12'b010100110101: aluop_sel = `ALUOP_BDEC;
|
12'b0x1x11xxxxxx: aluop_sel = `ALUOP_BOR;
|
12'b001011xxx110,
|
|
12'b001011xxxxxx,
|
|
12'b011011xxx110,
|
|
12'b011111xxx110: aluop_sel = `ALUOP_BOR;
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
12'b1xxx10111001: aluop_sel = `ALUOP_BSUB;
|
12'b000011001001,
|
12'b000011001001,
|
| Line 2181... |
Line 2558... |
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010011100011,
|
12'b010011100011,
|
12'b010111100011,
|
12'b010111100011,
|
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101,
|
12'b1xxx01001101,
|
//12'b1xxx01110100,
|
12'b1xxx10000010,
|
12'b1xxx100xx011,
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
|
12'b1xxx10101100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: aluop_sel = `ALUOP_PASS;
|
12'b1xxx10110100,
|
|
12'b1xxx10111000,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: aluop_sel = `ALUOP_PASS;
|
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
|
12'b0x1x00000xxx: aluop_sel = `ALUOP_RLC;
|
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
|
12'b0x1x00001xxx: aluop_sel = `ALUOP_RRC;
|
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
|
12'b0x1x00010xxx: aluop_sel = `ALUOP_RL;
|
12'b0x1x00011xxx: aluop_sel = `ALUOP_RR;
|
12'b0x1x00011xxx: aluop_sel = `ALUOP_RR;
|
12'b0x1x00100xxx: aluop_sel = `ALUOP_SLA;
|
12'b0x1x00100xxx: aluop_sel = `ALUOP_SLA;
|
| Line 2205... |
Line 2600... |
`WR1A: begin
|
`WR1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: aluop_sel = `ALUOP_PASS;
|
12'b1xxx10111010,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: aluop_sel = `ALUOP_PASS;
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_ADD;
|
default: aluop_sel = `ALUOP_ADD;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10011011,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111000: aluop_sel = `ALUOP_ADD;
|
12'b1xxx100xx011,
|
12'b1xxx10001011,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111011: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111011: aluop_sel = `ALUOP_ADD;
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b0001xxxxxxxx: aluop_sel = `ALUOP_APAS;
|
12'b0001xxxxxxxx: aluop_sel = `ALUOP_APAS;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_PASS;
|
default: aluop_sel = `ALUOP_PASS;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
| Line 2257... |
Line 2697... |
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
default: aluop_sel = `ALUOP_ADD;
|
default: aluop_sel = `ALUOP_ADD;
|
endcase
|
endcase
|
end
|
end
|
|
`PCA,
|
|
`PCO: aluop_sel = `ALUOP_ADD;
|
`IF1A: begin
|
`IF1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010: aluop_sel = `ALUOP_ADD;
|
12'b1xxx10111010,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: aluop_sel = `ALUOP_ADD;
|
|
12'b1xxx00011010,
|
|
12'b1xxx01010100,
|
|
12'b1xxx01010101,
|
|
12'b1xxx00110010,
|
|
12'b1xxx00110011,
|
|
12'b1xxx00xx0010,
|
|
12'b1xxx00xx0011: aluop_sel = `ALUOP_ADS;
|
12'b000010001xxx,
|
12'b000010001xxx,
|
12'b000011001110,
|
12'b000011001110,
|
12'b010x10001110: aluop_sel = `ALUOP_BADC;
|
12'b010x10001110: aluop_sel = `ALUOP_BADC;
|
12'b000010000xxx,
|
12'b000010000xxx,
|
12'b000011000110,
|
12'b000011000110,
|
12'b010x10000110,
|
12'b010x10000110,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b1xxx10111011: aluop_sel = `ALUOP_BADD;
|
12'b000010100xxx,
|
12'b000010100xxx,
|
| Line 2357... |
Line 2822... |
12'b010000101101,
|
12'b010000101101,
|
12'b010011100101,
|
12'b010011100101,
|
12'b010100100101,
|
12'b010100100101,
|
12'b010100101011,
|
12'b010100101011,
|
12'b010100101101,
|
12'b010100101101,
|
|
12'b1xxx10101100,
|
12'b010111100101: alua_sel = `ALUA_M1;
|
12'b010111100101: alua_sel = `ALUA_M1;
|
|
12'b1xxx10100100,
|
12'b010000100100,
|
12'b010000100100,
|
12'b010000101100,
|
12'b010000101100,
|
12'b010000100011,
|
12'b010000100011,
|
12'b010100100100,
|
12'b010100100100,
|
12'b010100101100,
|
12'b010100101100,
|
| Line 2388... |
Line 2855... |
12'b010100110110: alua_sel = `ALUA_IY;
|
12'b010100110110: alua_sel = `ALUA_IY;
|
default: alua_sel = `ALUA_M1;
|
default: alua_sel = `ALUA_M1;
|
endcase
|
endcase
|
end
|
end
|
`IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
|
`IF3A: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
|
`ADR1: alua_sel = (page_reg[2]) ? ((page_reg[0]) ? `ALUA_IY : `ALUA_IX) : `ALUA_M1;
|
`ADR1: begin
|
`ADR2: alua_sel = `ALUA_M1;
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b000011010011: alua_sel = `ALUA_M1;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: alua_sel = `ALUA_M1;
|
|
default: alua_sel = (page_reg[0]) ? `ALUA_IY : `ALUA_IX;
|
|
endcase
|
|
end
|
|
`ADR2: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx01100101: alua_sel = `ALUA_IX;
|
|
12'b1xxx01100110: alua_sel = `ALUA_IY;
|
|
default: alua_sel = `ALUA_M1;
|
|
endcase
|
|
end
|
`RD1B: begin
|
`RD1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
| Line 2402... |
Line 2882... |
endcase
|
endcase
|
end
|
end
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b1xxx100x1011,
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
|
12'b1xxx10101100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010: alua_sel = `ALUA_M1;
|
12'b1xxx10111010,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: alua_sel = `ALUA_M1;
|
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
endcase
|
endcase
|
end
|
end
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
| Line 2435... |
Line 2924... |
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
endcase
|
endcase
|
end
|
end
|
`WR1A: begin
|
`WR1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000100010,
|
12'b000011001101,
|
12'b000011100011,
|
12'b000011xxx100,
|
12'b010000100010,
|
12'b000011xx0101,
|
12'b010011100011,
|
12'b000011xxx111,
|
12'b010100100010,
|
12'b0001xxxxxxxx,
|
12'b010111100011,
|
12'b010011100101,
|
12'b1xxx01xx0011,
|
12'b010111100101,
|
12'b1xxx100x0011,
|
12'b1xxx01100101,
|
12'b1xxx10100000,
|
12'b1xxx01100110,
|
12'b1xxx10100011,
|
12'b1xxx10001010,
|
12'b1xxx10110000,
|
12'b1xxx10001011,
|
12'b1xxx10110011: alua_sel = `ALUA_ONE;
|
12'b1xxx10001100,
|
default: alua_sel = `ALUA_M1;
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10101000,
|
|
12'b1xxx10101011,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
|
12'b1xxx10111000,
|
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: alua_sel = `ALUA_M1;
|
|
default: alua_sel = `ALUA_ONE;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx1001x011,
|
12'b1xxx10000010,
|
12'b1xxx10110000,
|
12'b1xxx10000011,
|
12'b1xxx10110010,
|
12'b1xxx10000100,
|
12'b1xxx10110011,
|
12'b1xxx10001010,
|
12'b1xxx10111000,
|
12'b1xxx10001011,
|
12'b1xxx10111010,
|
12'b1xxx10001100,
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b1xxx10100000,
|
default: alua_sel = `ALUA_ONE;
|
12'b1xxx10100010,
|
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101000,
|
|
12'b1xxx10101010,
|
|
12'b1xxx10101011,
|
|
12'b1xxx10101100: alua_sel = `ALUA_ONE;
|
|
default: alua_sel = `ALUA_M1;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
|
12'b0001xxxxxxxx: alua_sel = `ALUA_INT;
|
12'b1xxx100x1011,
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: alua_sel = `ALUA_M1;
|
12'b000011xxx111: alua_sel = `ALUA_RST;
|
12'b000011xxx111: alua_sel = `ALUA_RST;
|
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx100xx011,
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
|
12'b1xxx10100100,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
|
12'b1xxx10110100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b1xxx10111011,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: alua_sel = `ALUA_M1;
|
default: alua_sel = `ALUA_ONE;
|
default: alua_sel = `ALUA_ONE;
|
endcase
|
endcase
|
end
|
end
|
`BLK1: begin
|
`BLK1: begin
|
alua_sel = (inst_reg[3]) ? `ALUA_M1 : `ALUA_ONE;
|
alua_sel = (inst_reg[3]) ? `ALUA_M1 : `ALUA_ONE;
|
| Line 2502... |
Line 3038... |
end
|
end
|
`PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2;
|
`PCA: alua_sel = (tflg_reg) ? `ALUA_ZER : `ALUA_M2;
|
`IF1A: begin
|
`IF1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
|
12'b0x1x01xxxxxx: alua_sel = `ALUA_BIT;
|
|
12'b1xxx00110010,
|
|
12'b1xxx00xx0010,
|
|
12'b1xxx01010101: alua_sel = `ALUA_IX;
|
|
12'b1xxx00110011,
|
|
12'b1xxx00xx0011,
|
|
12'b1xxx01010100: alua_sel = `ALUA_IY;
|
12'b1xxx00xxx000,
|
12'b1xxx00xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx100x1011,
|
12'b1xxx10001010,
|
|
12'b1xxx10001011,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011011,
|
|
12'b1xxx10011100,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
|
12'b1xxx10101100,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alua_sel = `ALUA_M1;
|
12'b1xxx10111011,
|
12'b1xxx100x0011,
|
12'b1xxx10111100,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011: alua_sel = `ALUA_M1;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000011,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010011,
|
|
12'b1xxx10010100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
|
12'b1xxx10100100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110010: alua_sel = `ALUA_ONE;
|
12'b1xxx10110010,
|
|
12'b1xxx10110100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011: alua_sel = `ALUA_ONE;
|
12'b1xxx01110100: alua_sel = `ALUA_TMP;
|
12'b1xxx01110100: alua_sel = `ALUA_TMP;
|
default: alua_sel = `ALUA_AA;
|
default: alua_sel = `ALUA_AA;
|
endcase
|
endcase
|
end
|
end
|
`INTA: alua_sel = `ALUA_M1;
|
`INTA: alua_sel = `ALUA_M1;
|
| Line 2597... |
Line 3157... |
12'b1xxx01000100,
|
12'b1xxx01000100,
|
12'b1xxx01000111,
|
12'b1xxx01000111,
|
12'b1xxx01001111: alub_sel = `ALUB_AA;
|
12'b1xxx01001111: alub_sel = `ALUB_AA;
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx000,
|
12'b1xxx01xxx001,
|
12'b1xxx01xxx001,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001100,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
12'b010000100011,
|
12'b010000100011,
|
| Line 2660... |
Line 3222... |
12'b010x0110x000,
|
12'b010x0110x000,
|
12'b1xxx00000100,
|
12'b1xxx00000100,
|
12'b0010xxxxx000: alub_sel = `ALUB_BB;
|
12'b0010xxxxx000: alub_sel = `ALUB_BB;
|
12'b010x0110x001,
|
12'b010x0110x001,
|
12'b1xxx00001100,
|
12'b1xxx00001100,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
12'b0010xxxxx001: alub_sel = `ALUB_CC;
|
12'b0010xxxxx001: alub_sel = `ALUB_CC;
|
12'b010x0110x010,
|
12'b010x0110x010,
|
12'b1xxx00010100,
|
12'b1xxx00010100,
|
12'b0010xxxxx010: alub_sel = `ALUB_DD;
|
12'b0010xxxxx010: alub_sel = `ALUB_DD;
|
12'b010x0110x011,
|
12'b010x0110x011,
|
| Line 2683... |
Line 3249... |
12'b1xxx01111100,
|
12'b1xxx01111100,
|
12'b1xxx0111x010: alub_sel = `ALUB_SP;
|
12'b1xxx0111x010: alub_sel = `ALUB_SP;
|
12'b010011100101,
|
12'b010011100101,
|
12'b010111100101: alub_sel = `ALUB_SP;
|
12'b010111100101: alub_sel = `ALUB_SP;
|
12'b010x00001001: alub_sel = `ALUB_BC;
|
12'b010x00001001: alub_sel = `ALUB_BC;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010,
|
12'b010x00011001: alub_sel = `ALUB_DE;
|
12'b010x00011001: alub_sel = `ALUB_DE;
|
12'b010000101001: alub_sel = `ALUB_IX;
|
12'b010000101001: alub_sel = `ALUB_IX;
|
12'b010100101001: alub_sel = `ALUB_IY;
|
12'b010100101001: alub_sel = `ALUB_IY;
|
12'b010x00111001: alub_sel = `ALUB_SP;
|
12'b010x00111001: alub_sel = `ALUB_SP;
|
default: alub_sel = `ALUB_HL;
|
default: alub_sel = `ALUB_HL;
|
| Line 2741... |
Line 3311... |
`ADR1: begin
|
`ADR1: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx01110100: alub_sel = `ALUB_CC;
|
12'b1xxx01110100: alub_sel = `ALUB_CC;
|
12'b000011010011,
|
12'b000011010011,
|
12'b000011011011: alub_sel = `ALUB_IO;
|
12'b000011011011: alub_sel = `ALUB_IO;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: alub_sel = `ALUB_SP;
|
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
|
12'b0001xxxxxxxx: alub_sel = `ALUB_TMP;
|
default: alub_sel = `ALUB_DIN;
|
default: alub_sel = `ALUB_DIN;
|
endcase
|
endcase
|
end
|
end
|
`ADR2: begin
|
`ADR2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000000010,
|
12'b000000000010,
|
12'b000000010010,
|
12'b000000010010,
|
12'b000000110010,
|
12'b000000110010,
|
12'b000011010011: alub_sel = `ALUB_AA;
|
12'b000011010011: alub_sel = `ALUB_AA;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111001: alub_sel = `ALUB_BC;
|
12'b1xxx10111001: alub_sel = `ALUB_BC;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: alub_sel = `ALUB_DIN;
|
12'b010000100010: alub_sel = `ALUB_IX;
|
12'b010000100010: alub_sel = `ALUB_IX;
|
12'b010011100101: alub_sel = `ALUB_IXH;
|
12'b010011100101: alub_sel = `ALUB_IXH;
|
|
12'b010000111111,
|
|
12'b010100111110,
|
|
12'b1xxx00111111: alub_sel = `ALUB_IXL;
|
12'b010100100010: alub_sel = `ALUB_IY;
|
12'b010100100010: alub_sel = `ALUB_IY;
|
12'b010111100101: alub_sel = `ALUB_IYH;
|
12'b010111100101: alub_sel = `ALUB_IYH;
|
|
12'b010000111110,
|
|
12'b010100111111,
|
|
12'b1xxx00111110: alub_sel = `ALUB_IYL;
|
12'b000011xxx111: alub_sel = `ALUB_PCH;
|
12'b000011xxx111: alub_sel = `ALUB_PCH;
|
12'b000001xxx000,
|
12'b000001xxx000,
|
12'b010x01110000,
|
12'b010x01110000,
|
12'b1xxx00000001,
|
12'b1xxx00000001,
|
12'b1xxx01000001: alub_sel = `ALUB_BB;
|
12'b1xxx01000001: alub_sel = `ALUB_BB;
|
|
12'b010000001111,
|
|
12'b010100001111,
|
|
12'b1xxx00001111,
|
12'b000001xxx001,
|
12'b000001xxx001,
|
12'b010x01110001,
|
12'b010x01110001,
|
12'b1xxx01110100,
|
12'b1xxx01110100,
|
12'b1xxx00001001,
|
12'b1xxx00001001,
|
12'b1xxx01001001: alub_sel = `ALUB_CC;
|
12'b1xxx01001001: alub_sel = `ALUB_CC;
|
12'b000001xxx010,
|
12'b000001xxx010,
|
12'b010x01110010,
|
12'b010x01110010,
|
12'b1xxx00010001,
|
12'b1xxx00010001,
|
12'b1xxx01010001: alub_sel = `ALUB_DD;
|
12'b1xxx01010001: alub_sel = `ALUB_DD;
|
|
12'b010000011111,
|
|
12'b010100011111,
|
|
12'b1xxx00011111,
|
12'b000001xxx011,
|
12'b000001xxx011,
|
12'b010x01110011,
|
12'b010x01110011,
|
12'b1xxx00011001,
|
12'b1xxx00011001,
|
12'b1xxx01011001: alub_sel = `ALUB_EE;
|
12'b1xxx01011001: alub_sel = `ALUB_EE;
|
12'b000001xxx100,
|
12'b000001xxx100,
|
12'b010x01110100,
|
12'b010x01110100,
|
12'b1xxx00100001,
|
12'b1xxx00100001,
|
12'b1xxx01100001: alub_sel = `ALUB_HH;
|
12'b1xxx01100001: alub_sel = `ALUB_HH;
|
|
12'b010000101111,
|
|
12'b010100101111,
|
|
12'b1xxx00101111,
|
12'b000001xxx101,
|
12'b000001xxx101,
|
12'b010x01110101,
|
12'b010x01110101,
|
12'b1xxx00101001,
|
12'b1xxx00101001,
|
12'b1xxx01101001: alub_sel = `ALUB_LL;
|
12'b1xxx01101001: alub_sel = `ALUB_LL;
|
12'b000001xxx111,
|
12'b000001xxx111,
|
| Line 2809... |
Line 3414... |
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
12'b000011000101: alub_sel = `ALUB_BB;
|
12'b000011000101: alub_sel = `ALUB_BB;
|
12'b000011010101: alub_sel = `ALUB_DD;
|
12'b000011010101: alub_sel = `ALUB_DD;
|
12'b000011100101: alub_sel = `ALUB_HH;
|
12'b000011100101: alub_sel = `ALUB_HH;
|
12'b000011110101: alub_sel = `ALUB_AA;
|
12'b000011110101: alub_sel = `ALUB_AA;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: alub_sel = `ALUB_TMP;
|
default: alub_sel = `ALUB_HL;
|
default: alub_sel = `ALUB_HL;
|
endcase
|
endcase
|
end
|
end
|
`RD1A: begin
|
`RD1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110001,
|
12'b1xxx10110001,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111001,
|
12'b1xxx10111001,
|
12'b1xxx10111010: alub_sel = `ALUB_HL;
|
12'b1xxx10111010: alub_sel = `ALUB_HL;
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
12'b000000101010,
|
12'b000000101010,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010000101010,
|
12'b010000101010,
|
12'b010100101010,
|
12'b010100101010,
|
12'b1xxx01xx1011: alub_sel = `ALUB_TMP;
|
12'b1xxx01xx1011: alub_sel = `ALUB_TMP;
|
| Line 2842... |
Line 3474... |
endcase
|
endcase
|
end
|
end
|
`RD1B: alub_sel = `ALUB_DIN;
|
`RD1B: alub_sel = `ALUB_DIN;
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
12'b1xxx10111011: alub_sel = `ALUB_BC;
|
12'b1xxx01110100,
|
12'b1xxx01110100,
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010,
|
12'b001010xxxxxx,
|
12'b001010xxxxxx,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
| Line 2880... |
Line 3528... |
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000011100011: alub_sel = `ALUB_HL;
|
12'b000011100011: alub_sel = `ALUB_HL;
|
12'b010011100011: alub_sel = `ALUB_IX;
|
12'b010011100011: alub_sel = `ALUB_IX;
|
12'b010111100011: alub_sel = `ALUB_IY;
|
12'b010111100011: alub_sel = `ALUB_IY;
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000xx0111,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100xx0111,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00xx0111,
|
12'b000000001010,
|
12'b000000001010,
|
12'b000000011010,
|
12'b000000011010,
|
12'b000000101010,
|
12'b000000101010,
|
12'b000000111010,
|
12'b000000111010,
|
12'b000001xxxxxx,
|
12'b000001xxxxxx,
|
| Line 2932... |
Line 3589... |
default: alub_sel = `ALUB_DIN;
|
default: alub_sel = `ALUB_DIN;
|
endcase
|
endcase
|
end
|
end
|
`WR1A: begin
|
`WR1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100: alub_sel = `ALUB_BB;
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001100,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: alub_sel = `ALUB_CC;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: alub_sel = `ALUB_DE;
|
|
12'b1xxx00111110,
|
|
12'b1xxx00111111,
|
|
12'b1xxx00xx1111,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111011: alub_sel = `ALUB_HL;
|
12'b1xxx10111011: alub_sel = `ALUB_HL;
|
|
12'b010000111110,
|
|
12'b010000111111,
|
|
12'b010000xx1111,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx1111,
|
12'b000000100010,
|
12'b000000100010,
|
12'b010000100010,
|
12'b010000100010,
|
12'b010100100010,
|
12'b010100100010,
|
12'b1xxx01xx0011: alub_sel = `ALUB_TMP;
|
12'b1xxx01xx0011: alub_sel = `ALUB_TMP;
|
default: alub_sel = `ALUB_SP;
|
default: alub_sel = `ALUB_SP;
|
endcase
|
endcase
|
end
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
|
12'b010000001111,
|
|
12'b010100001111,
|
|
12'b1xxx00001111,
|
12'b1xxx1001x011,
|
12'b1xxx1001x011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: alub_sel = `ALUB_BC;
|
12'b1xxx10111000: alub_sel = `ALUB_BC;
|
|
12'b010000011111,
|
|
12'b010100011111,
|
|
12'b1xxx00011111: alub_sel = `ALUB_DD;
|
|
12'b010000101111,
|
|
12'b010100101111,
|
|
12'b1xxx00101111,
|
12'b000000100010,
|
12'b000000100010,
|
12'b000011100011: alub_sel = `ALUB_HH;
|
12'b000011100011: alub_sel = `ALUB_HH;
|
12'b010011100101: alub_sel = `ALUB_IX;
|
12'b010011100101: alub_sel = `ALUB_IX;
|
|
12'b010000111111,
|
|
12'b010100111110,
|
|
12'b1xxx00111111,
|
12'b010000100010,
|
12'b010000100010,
|
12'b010011100011: alub_sel = `ALUB_IXH;
|
12'b010011100011: alub_sel = `ALUB_IXH;
|
12'b010111100101: alub_sel = `ALUB_IY;
|
12'b010111100101: alub_sel = `ALUB_IY;
|
|
12'b010000111110,
|
|
12'b010100111111,
|
|
12'b1xxx00111110,
|
12'b010100100010,
|
12'b010100100010,
|
12'b010111100011: alub_sel = `ALUB_IYH;
|
12'b010111100011: alub_sel = `ALUB_IYH;
|
12'b1xxx01000011: alub_sel = `ALUB_BC;
|
12'b1xxx01000011: alub_sel = `ALUB_BC;
|
12'b1xxx01010011: alub_sel = `ALUB_DE;
|
12'b1xxx01010011: alub_sel = `ALUB_DE;
|
12'b1xxx01100011: alub_sel = `ALUB_HL;
|
12'b1xxx01100011: alub_sel = `ALUB_HL;
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
12'b1xxx01110011: alub_sel = `ALUB_SP;
|
12'b000011000101: alub_sel = `ALUB_BC;
|
12'b000011000101: alub_sel = `ALUB_BC;
|
12'b000011010101: alub_sel = `ALUB_DE;
|
12'b000011010101: alub_sel = `ALUB_DE;
|
12'b000011100101: alub_sel = `ALUB_HL;
|
12'b000011100101: alub_sel = `ALUB_HL;
|
12'b000011110101: alub_sel = `ALUB_AF;
|
12'b000011110101: alub_sel = `ALUB_AF;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: alub_sel = `ALUB_TMP;
|
default: alub_sel = `ALUB_PC;
|
default: alub_sel = `ALUB_PC;
|
endcase
|
endcase
|
end
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: alub_sel = `ALUB_CC;
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
12'b1xxx10111010: alub_sel = `ALUB_BC;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: alub_sel = `ALUB_DE;
|
12'b000011001101,
|
12'b000011001101,
|
12'b000011xxx100: alub_sel = `ALUB_DIN;
|
12'b000011xxx100: alub_sel = `ALUB_DIN;
|
default: alub_sel = `ALUB_HL;
|
default: alub_sel = `ALUB_HL;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: alub_sel = `ALUB_BC;
|
12'b1xxx10111000: alub_sel = `ALUB_BC;
|
default: alub_sel = `ALUB_PC;
|
default: alub_sel = `ALUB_PC;
|
| Line 3019... |
Line 3754... |
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
12'b1xxx10111011: alub_sel = `ALUB_BB;
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
12'b1xxx100xx011: alub_sel = `ALUB_CC;
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
12'b1xxx10111000: alub_sel = `ALUB_DE;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10110010: alub_sel = `ALUB_HL;
|
12'b1xxx10110010,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: alub_sel = `ALUB_HL;
|
default: alub_sel = `ALUB_DIN;
|
default: alub_sel = `ALUB_DIN;
|
endcase
|
endcase
|
end
|
end
|
`INTA: alub_sel = `ALUB_SP;
|
`INTA: alub_sel = `ALUB_SP;
|
`INTB: alub_sel = `ALUB_PCH;
|
`INTB: alub_sel = `ALUB_PCH;
|
| Line 3074... |
Line 3825... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`ADR2: begin
|
`ADR2: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100: wr_addr = `WREG_HL;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b010011100101,
|
12'b010011100101,
|
12'b010111100101: wr_addr = `WREG_SP;
|
12'b010111100101: wr_addr = `WREG_SP;
|
|
12'b010000110001,
|
|
12'b010000110111,
|
|
12'b010000111110,
|
|
12'b010000111111,
|
|
12'b010000xx0111,
|
|
12'b010000xx1111,
|
|
12'b010100110001,
|
|
12'b010100110111,
|
|
12'b010100111110,
|
|
12'b010100111111,
|
|
12'b010100xx0111,
|
|
12'b010100xx1111,
|
12'b000000100010,
|
12'b000000100010,
|
12'b000000101010,
|
12'b000000101010,
|
12'b010000100010,
|
12'b010000100010,
|
12'b010000101010,
|
12'b010000101010,
|
12'b010000110100,
|
12'b010000110100,
|
| Line 3095... |
Line 3862... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`RD1A: begin
|
`RD1A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 3129... |
Line 3910... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100001,
|
12'b1xxx10100001,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101001,
|
12'b1xxx10101001,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
| Line 3152... |
Line 3949... |
endcase
|
endcase
|
end
|
end
|
`RD2B: begin
|
`RD2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b1xxx100xx011: wr_addr = `WREG_CC;
|
12'b1xxx100xx011: wr_addr = `WREG_CC;
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
12'b1xxx10111000: wr_addr = `WREG_DE;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: wr_addr = `WREG_HL;
|
12'b1xxx10111010,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: wr_addr = `WREG_HL;
|
12'b000011001001,
|
12'b000011001001,
|
12'b000011xxx000,
|
12'b000011xxx000,
|
12'b000011xx0001,
|
12'b000011xx0001,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
12'b010011100001,
|
12'b010011100001,
|
| Line 3171... |
Line 3980... |
12'b1xxx01000101,
|
12'b1xxx01000101,
|
12'b1xxx01001101: wr_addr = `WREG_SP;
|
12'b1xxx01001101: wr_addr = `WREG_SP;
|
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
|
`WR1A: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110: wr_addr = `WREG_TMP;
|
|
default: wr_addr = `WREG_NUL;
|
|
endcase
|
|
end
|
`WR1B: begin
|
`WR1B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100: wr_addr = `WREG_BB;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: wr_addr = `WREG_CC;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100: wr_addr = `WREG_DE;
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111000,
|
12'b1xxx10111000,
|
12'b1xxx10111011: wr_addr = `WREG_HL;
|
12'b1xxx10111011: wr_addr = `WREG_HL;
|
|
12'b1xxx01100101,
|
|
12'b1xxx01100110,
|
12'b000011001101,
|
12'b000011001101,
|
12'b000011xxx100,
|
12'b000011xxx100,
|
12'b000011xxx111,
|
12'b000011xxx111,
|
12'b000011xx0101,
|
12'b000011xx0101,
|
12'b0001xxxxxxxx,
|
12'b0001xxxxxxxx,
|
| Line 3194... |
Line 4026... |
default: wr_addr = `WREG_NUL;
|
default: wr_addr = `WREG_NUL;
|
endcase
|
endcase
|
end
|
end
|
`WR2B: begin
|
`WR2B: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10011010: wr_addr = `WREG_CC;
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011100: wr_addr = `WREG_DE;
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001011,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
| Line 3246... |
Line 4092... |
12'b000011100110,
|
12'b000011100110,
|
12'b000011101110,
|
12'b000011101110,
|
12'b000011110110,
|
12'b000011110110,
|
12'b001000xxx111,
|
12'b001000xxx111,
|
12'b00101xxxx111,
|
12'b00101xxxx111,
|
//12'b011x00xxx111,
|
|
//12'b011x1xxxx111,
|
|
12'b010010000100,
|
12'b010010000100,
|
12'b010010000101,
|
12'b010010000101,
|
12'b010010000110,
|
12'b010010000110,
|
12'b010010001100,
|
12'b010010001100,
|
12'b010010001101,
|
12'b010010001101,
|
| Line 3304... |
Line 4148... |
12'b00000000010x,
|
12'b00000000010x,
|
12'b000000000110,
|
12'b000000000110,
|
12'b000001000xxx,
|
12'b000001000xxx,
|
12'b001000xxx000,
|
12'b001000xxx000,
|
12'b00101xxxx000,
|
12'b00101xxxx000,
|
//12'b011x00xxx000,
|
|
// 12'b011x1xxxx000,
|
|
12'b010x0100010x,
|
12'b010x0100010x,
|
12'b010x01000110,
|
12'b010x01000110,
|
12'b1xxx0x000000,
|
12'b1xxx0x000000,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
12'b1xxx10110011,
|
12'b1xxx10110011,
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
12'b1xxx10111011: wr_addr = `WREG_BB;
|
|
12'b010000000111,
|
|
12'b010100000111,
|
|
12'b1xxx00000111,
|
|
12'b1xxx00000010,
|
|
12'b1xxx00000011,
|
12'b000000000001,
|
12'b000000000001,
|
12'b00000000x011,
|
12'b00000000x011,
|
12'b000011000001,
|
12'b000011000001,
|
12'b1xxx01001100,
|
12'b1xxx01001100,
|
12'b1xxx01001011: wr_addr = `WREG_BC;
|
12'b1xxx01001011: wr_addr = `WREG_BC;
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
12'b00000000110x,
|
12'b00000000110x,
|
12'b000000001110,
|
12'b000000001110,
|
12'b000001001xxx,
|
12'b000001001xxx,
|
12'b001000xxx001,
|
12'b001000xxx001,
|
12'b00101xxxx001,
|
12'b00101xxxx001,
|
//12'b011x00xxx001,
|
|
//12'b011x1xxxx001,
|
|
12'b010x0100110x,
|
12'b010x0100110x,
|
12'b010x01001110,
|
12'b010x01001110,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx0x001000: wr_addr = `WREG_CC;
|
12'b1xxx0x001000: wr_addr = `WREG_CC;
|
12'b00000001010x,
|
12'b00000001010x,
|
12'b000000010110,
|
12'b000000010110,
|
12'b000001010xxx,
|
12'b000001010xxx,
|
12'b001000xxx010,
|
12'b001000xxx010,
|
12'b00101xxxx010,
|
12'b00101xxxx010,
|
//12'b011x00xxx010,
|
|
//12'b011x1xxxx010,
|
|
12'b010x0101010x,
|
12'b010x0101010x,
|
12'b010x01010110,
|
12'b010x01010110,
|
12'b1xxx0x010000: wr_addr = `WREG_DD;
|
12'b1xxx0x010000: wr_addr = `WREG_DD;
|
|
12'b010000010111,
|
|
12'b010100010111,
|
|
12'b1xxx00010111,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx00010010,
|
|
12'b1xxx00010011,
|
12'b000011010001,
|
12'b000011010001,
|
12'b00000001x011,
|
12'b00000001x011,
|
12'b000000010001,
|
12'b000000010001,
|
12'b1xxx01011100,
|
12'b1xxx01011100,
|
12'b1xxx01011011,
|
12'b1xxx01011011,
|
| Line 3354... |
Line 4206... |
12'b00000001110x,
|
12'b00000001110x,
|
12'b000000011110,
|
12'b000000011110,
|
12'b000001011xxx,
|
12'b000001011xxx,
|
12'b001000xxx011,
|
12'b001000xxx011,
|
12'b00101xxxx011,
|
12'b00101xxxx011,
|
//12'b011x00xxx011,
|
|
//12'b011x1xxxx011,
|
|
12'b010x0101110x,
|
12'b010x0101110x,
|
12'b010x01011110,
|
12'b010x01011110,
|
12'b1xxx0x011000: wr_addr = `WREG_EE;
|
12'b1xxx0x011000: wr_addr = `WREG_EE;
|
12'b00000010010x,
|
12'b00000010010x,
|
12'b000000100110,
|
12'b000000100110,
|
12'b000001100xxx,
|
12'b000001100xxx,
|
12'b001000xxx100,
|
12'b001000xxx100,
|
12'b00101xxxx100,
|
12'b00101xxxx100,
|
//12'b011x00xxx100,
|
|
//12'b011x1xxxx100,
|
|
12'b010x01100110,
|
12'b010x01100110,
|
12'b1xxx0x100000: wr_addr = `WREG_HH;
|
12'b1xxx0x100000: wr_addr = `WREG_HH;
|
|
12'b010000100111,
|
|
12'b010100100111,
|
|
12'b1xxx00100010,
|
|
12'b1xxx00100011,
|
|
12'b1xxx00100111,
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
12'b000000100001,
|
12'b000000100001,
|
12'b000000101010,
|
12'b000000101010,
|
12'b00000010x011,
|
12'b00000010x011,
|
12'b000000xx1001,
|
12'b000000xx1001,
|
12'b000011100001,
|
12'b000011100001,
|
| Line 3381... |
Line 4242... |
12'b1xxx01xx0010,
|
12'b1xxx01xx0010,
|
12'b1xxx01xx1010,
|
12'b1xxx01xx1010,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10110010,
|
12'b1xxx10110010,
|
12'b1xxx10111010: wr_addr = `WREG_HL;
|
12'b1xxx10111010,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11001010: wr_addr = `WREG_HL;
|
12'b1xxx01000111: wr_addr = `WREG_II;
|
12'b1xxx01000111: wr_addr = `WREG_II;
|
|
12'b010000110111,
|
|
12'b010100110001,
|
|
12'b1xxx00110111,
|
|
12'b1xxx00110010,
|
|
12'b1xxx01010100,
|
12'b010000100001,
|
12'b010000100001,
|
12'b010000100011,
|
12'b010000100011,
|
12'b010000101010,
|
12'b010000101010,
|
12'b010000101011,
|
12'b010000101011,
|
12'b010000xx1001,
|
12'b010000xx1001,
|
| Line 3402... |
Line 4270... |
12'b010000101101,
|
12'b010000101101,
|
12'b010000101110,
|
12'b010000101110,
|
12'b0100011010xx,
|
12'b0100011010xx,
|
12'b01000110110x,
|
12'b01000110110x,
|
12'b010001101111: wr_addr = `WREG_IXL;
|
12'b010001101111: wr_addr = `WREG_IXL;
|
|
12'b010000110001,
|
|
12'b010100110111,
|
|
12'b1xxx00110110,
|
|
12'b1xxx00110011,
|
|
12'b1xxx01010101,
|
12'b010100100001,
|
12'b010100100001,
|
12'b010100100011,
|
12'b010100100011,
|
12'b010100101010,
|
12'b010100101010,
|
12'b010100101011,
|
12'b010100101011,
|
12'b010100xx1001,
|
12'b010100xx1001,
|
| Line 3426... |
Line 4299... |
12'b00000010110x,
|
12'b00000010110x,
|
12'b000000101110,
|
12'b000000101110,
|
12'b000001101xxx,
|
12'b000001101xxx,
|
12'b001000xxx101,
|
12'b001000xxx101,
|
12'b00101xxxx101,
|
12'b00101xxxx101,
|
//12'b011x00xxx101,
|
|
//12'b011x1xxxx101,
|
|
12'b010x01101110,
|
12'b010x01101110,
|
12'b1xxx0x101000: wr_addr = `WREG_LL;
|
12'b1xxx0x101000: wr_addr = `WREG_LL;
|
12'b1xxx01001111: wr_addr = `WREG_RR;
|
12'b1xxx01001111: wr_addr = `WREG_RR;
|
12'b000000110001,
|
12'b000000110001,
|
12'b00000011x011,
|
12'b00000011x011,
|
| Line 3590... |
Line 4461... |
always @ (inst_reg or page_reg or state_reg) begin
|
always @ (inst_reg or page_reg or state_reg) begin
|
casex (state_reg) //synopsys parallel_case
|
casex (state_reg) //synopsys parallel_case
|
`RD1A,
|
`RD1A,
|
`RD2A: begin
|
`RD2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
12'b1xxx100xx011,
|
12'b1xxx100xx011,
|
12'b1xxx10100010,
|
12'b1xxx10100010,
|
12'b1xxx10100011,
|
12'b1xxx10100011,
|
12'b1xxx10101010,
|
12'b1xxx10101010,
|
12'b1xxx10101011,
|
12'b1xxx10101011,
|
| Line 3602... |
Line 4487... |
12'b1xxx10111010,
|
12'b1xxx10111010,
|
12'b1xxx10111011: zflg_en = 1'b1;
|
12'b1xxx10111011: zflg_en = 1'b1;
|
default: zflg_en = 1'b0;
|
default: zflg_en = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
|
`WR1B: begin
|
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100: zflg_en = 1'b1;
|
|
default: zflg_en = 1'b0;
|
|
endcase
|
|
end
|
`WR2A: begin
|
`WR2A: begin
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
casex ({page_reg, inst_reg}) //synopsys parallel_case
|
12'b000000110100,
|
12'b000000110100,
|
12'b000000110101,
|
12'b000000110101,
|
12'b001000xxxxxx,
|
12'b001000xxxxxx,
|
| Line 4129... |
Line 5021... |
12'b1xxx01xx1010,
|
12'b1xxx01xx1010,
|
12'b1xxx10100000,
|
12'b1xxx10100000,
|
12'b1xxx10101000,
|
12'b1xxx10101000,
|
12'b1xxx10110000,
|
12'b1xxx10110000,
|
12'b1xxx10111000: nflg_ctl = `NFLG_0;
|
12'b1xxx10111000: nflg_ctl = `NFLG_0;
|
|
12'b1xxx10000010,
|
|
12'b1xxx10000100,
|
|
12'b1xxx10001010,
|
|
12'b1xxx10001100,
|
|
12'b1xxx10010010,
|
|
12'b1xxx10010100,
|
|
12'b1xxx10011010,
|
|
12'b1xxx10011100,
|
|
12'b1xxx10100100,
|
|
12'b1xxx10101100,
|
|
12'b1xxx10110100,
|
|
12'b1xxx10111100,
|
|
12'b1xxx11000010,
|
|
12'b1xxx11000011,
|
|
12'b1xxx11001010,
|
|
12'b1xxx11001011,
|
12'b000000101111,
|
12'b000000101111,
|
12'b000000110101,
|
12'b000000110101,
|
12'b000000xxx101,
|
12'b000000xxx101,
|
12'b000010010110,
|
12'b000010010110,
|
12'b000010010xxx,
|
12'b000010010xxx,
|
