| Line 68... |
Line 68... |
o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input
|
o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input
|
|
|
i_SSR : in std_logic; -- Synchronous Set/Reset Input
|
i_SSR : in std_logic; -- Synchronous Set/Reset Input
|
|
|
i_clock_r : in std_logic; -- Read Clock
|
i_clock_r : in std_logic; -- Read Clock
|
|
i_EN_r : in std_logic;
|
i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input
|
i_ADDR_r : in std_logic_vector(12 downto 0); -- Read 13-bit Address Input
|
o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output
|
o_DO_r : out std_logic_vector(7 downto 0) -- Read 8-bit Data Output
|
);
|
);
|
end chars_RAM;
|
end chars_RAM;
|
|
|
| Line 159... |
Line 160... |
)
|
)
|
port map(
|
port map(
|
-- read
|
-- read
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIPA => (others => '0'),
|
DIPA => (others => '0'),
|
ENA => '1', -- RAM Enable Input
|
ENA => i_EN_r, -- RAM Enable Input
|
WEA => '0', -- Write Enable Input
|
WEA => '0', -- Write Enable Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
CLKA => i_clock_r, -- Clock
|
CLKA => i_clock_r, -- Clock
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
DOA => s0_DO_r, -- 8-bit Data Output
|
DOA => s0_DO_r, -- 8-bit Data Output
|
| Line 257... |
Line 258... |
)
|
)
|
port map(
|
port map(
|
-- read
|
-- read
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIPA => (others => '0'),
|
DIPA => (others => '0'),
|
ENA => '1', -- RAM Enable Input
|
ENA => i_EN_r, -- RAM Enable Input
|
WEA => '0', -- Write Enable Input
|
WEA => '0', -- Write Enable Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
CLKA => i_clock_r, -- Clock
|
CLKA => i_clock_r, -- Clock
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
DOA => s1_DO_r, -- 8-bit Data Output
|
DOA => s1_DO_r, -- 8-bit Data Output
|
| Line 355... |
Line 356... |
)
|
)
|
port map(
|
port map(
|
-- read
|
-- read
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIPA => (others => '0'),
|
DIPA => (others => '0'),
|
ENA => '1', -- RAM Enable Input
|
ENA => i_EN_r, -- RAM Enable Input
|
WEA => '0', -- Write Enable Input
|
WEA => '0', -- Write Enable Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
CLKA => i_clock_r, -- Clock
|
CLKA => i_clock_r, -- Clock
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
DOA => s2_DO_r, -- 8-bit Data Output
|
DOA => s2_DO_r, -- 8-bit Data Output
|
| Line 453... |
Line 454... |
)
|
)
|
port map(
|
port map(
|
-- read
|
-- read
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIA => (others => '0'), -- 2-bit Data Input
|
DIPA => (others => '0'),
|
DIPA => (others => '0'),
|
ENA => '1', -- RAM Enable Input
|
ENA => i_EN_r, -- RAM Enable Input
|
WEA => '0', -- Write Enable Input
|
WEA => '0', -- Write Enable Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
SSRA => i_SSR, -- Synchronous Set/Reset Input
|
CLKA => i_clock_r, -- Clock
|
CLKA => i_clock_r, -- Clock
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
ADDRA => i_ADDR_r(12 downto 2), -- 11-bit Address Input
|
DOA => s3_DO_r, -- 8-bit Data Output
|
DOA => s3_DO_r, -- 8-bit Data Output
|
