A-Z80
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A-Z80
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A conceptual implementation of the Z80 CPU
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A conceptual implementation of the Z80 CPU
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for Altera, Xilinx and Lattice FPGAs
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for Altera, Xilinx and Lattice FPGAs
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This project is described in more details at www.baltazarstudios.com
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This project is described in more details at https://baltazarstudios.com
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For additional information, read 'Quick Start' and 'Users Guide' documents
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For additional information, read 'Quick Start' and 'Users Guide' documents
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in the 'docs' folder. Also read a 'readme.txt' file in each of the folders.
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in the 'docs' folder. Also read a 'readme.txt' file in each of the folders.
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Prerequisites
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Prerequisites
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=============
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=============
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* Altera Quartus and Modelsim (free web editions) OR
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* Altera Quartus and Modelsim (free web editions) OR
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* Xilinx ISE (free Webpack edition) OR
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* Xilinx ISE (free Webpack edition) OR
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* Lattice ICECube toolchain from Synopsis (Lattice tested by JuanS)
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* Lattice ICECube toolchain from Synopsis (Lattice tested by JuanS)
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* Python 3.5 or newer
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* Python 3.5 or newer
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Importing A-Z80 into your project
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Importing A-Z80 into your project
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=================================
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=================================
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If you want to use A-Z80 in your own project, run "export.py" script which
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If you want to use A-Z80 in your own project, run "export.py" script which
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will copy only files that are needed. Do not manually pick and copy files.
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will copy only the files that are needed. Do not manually pick and copy files.
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Folder content
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Folder layout
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==============
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=============
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"cpu" folder contains all CPU functional blocks and top-level modules:
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"cpu" folder contains CPU functional blocks and all top-level modules:
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alu ALU block, ALU control and flags logic
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alu ALU block, ALU control and flags logic
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bus data bus switches, pin logic, address latch and incrementer
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bus data bus switches, pin logic, address latch and incrementer
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control PLA decoder, the sequencer and other control blocks
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control PLA decoder, the sequencer and other control blocks
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registers CPU register file and the register control logic
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registers CPU register file and the register control logic
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toplevel top level core, interfaces and test code
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toplevel top level core, interfaces and test code
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"host" folder integrates the A-Z80 CPU into several fully functional designs:
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"host" folder integrates the A-Z80 CPU into several fully functional designs:
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"basic_de1" contains a simplified board consisting of A-Z80 CPU, memory
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"basic_de1" contains a simplified board consisting of A-Z80 CPU, memory
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and UART modules that can run small Z80 programs on Altera DE1
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and UART modules that can run small Z80 programs on Altera DE1
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"basic_nexys3" contains the same example project but for Xilinx Nexys3 board
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"basic_nexys3" contains the same example project but for Xilinx Nexys3 board
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"zxspectrum_de1" contains a simple implementation of the Sinclair ZX Spectrum
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"zxspectrum_de1" contains a simple implementation of the Sinclair ZX Spectrum
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for Altera DE1 board
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for Altera DE1 board
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"tools", "resources" contain various tools related to the project; reverse
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"tools", "resources" contain various tools related to the project; reverse
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engineering Z80, design verification and testing.
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engineering of the real Z80, design verification and testing.
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Email me if you have any questions, issues or you want to use A-Z80 or any of
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Email me if you have any questions, issues or you want to use A-Z80 or any of
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the files herein; I'd like to hear from you,
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the files within this project. I'd like to hear from you,
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Goran Devic
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Goran Devic
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gdevic@yahoo.com
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gdevic@yahoo.com
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This project and each file therein is covered under the GNU GPL2.0 license.
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This project and each file therein is covered under the GNU GPL2.0 license.
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It basically states that anyone is free to use it and distribute it, but the full
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It basically states that anyone is free to use it and distribute it, but the full
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source needs to be available under the same terms.
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source needs to be available under the same terms.
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