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module aeMB2_intu (/*AUTOARG*/
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module aeMB2_intu (/*AUTOARG*/
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// Outputs
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// Outputs
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mem_ex, bpc_ex, alu_ex, alu_mx, msr_ex, sfr_mx,
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mem_ex, bpc_ex, alu_ex, alu_mx, msr_ex, sfr_mx,
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// Inputs
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// Inputs
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opc_of, opa_of, opb_of, opd_of, imm_of, rd_of, ra_of, gclk, grst,
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exc_dwb, exc_ill, rpc_ex, opc_of, opa_of, opb_of, opd_of, imm_of,
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dena, gpha
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rd_of, ra_of, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_DWB = 32;
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parameter AEMB_DWB = 32;
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parameter AEMB_IWB = 32;
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parameter AEMB_IWB = 32;
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parameter AEMB_HTX = 1;
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parameter AEMB_HTX = 1;
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Line 42... |
output [31:2] bpc_ex;
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output [31:2] bpc_ex;
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output [31:0] alu_ex,
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output [31:0] alu_ex,
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alu_mx;
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alu_mx;
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input [1:0] exc_dwb;
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input exc_ill;
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input [31:2] rpc_ex;
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//input [2:0] mux_of;
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//input [2:0] mux_of;
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input [5:0] opc_of;
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input [5:0] opc_of;
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input [31:0] opa_of;
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input [31:0] opa_of;
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input [31:0] opb_of;
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input [31:0] opb_of;
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input [31:0] opd_of;
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input [31:0] opd_of;
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Line 93... |
rMSR_ITE,
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rMSR_ITE,
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rMSR_BIP,
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rMSR_BIP,
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rMSR_IE,
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rMSR_IE,
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rMSR_BE;
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rMSR_BE;
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reg [31:0] rEAR,
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rEAR_C;
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reg [1:0] rESR,
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rESR_C;
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// Infer a ADD with carry cell because ADDSUB cannot be inferred
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// Infer a ADD with carry cell because ADDSUB cannot be inferred
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// across technologies.
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// across technologies.
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reg [31:0] add_ex;
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reg [31:0] add_ex;
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reg add_c;
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reg add_c;
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Line 181... |
MSR bits
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MSR bits
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31 - CC (carry copy)
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31 - CC (carry copy)
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30 - HTE (hardware thread enabled)
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30 - HTE (hardware thread enabled)
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29 - PHA (current phase)
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29 - PHA (current phase)
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9 - EIP (exception in progress)
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8 - EE (exception enable)
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7 - DTE (data cache enable)
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7 - DTE (data cache enable)
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5 - ITE (instruction cache enable)
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5 - ITE (instruction cache enable)
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4 - MTX (hardware mutex bit)
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4 - MTX (hardware mutex bit)
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3 - BIP (break in progress)
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3 - BIP (break in progress)
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2 - C (carry flag)
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2 - C (carry flag)
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Line 230... |
wire fBRKE = (opc_of == 6'o56) & (ra_of[4:0] == 5'hE);
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wire fBRKE = (opc_of == 6'o56) & (ra_of[4:0] == 5'hE);
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wire fMOV = (opc_of == 6'o45);
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wire fMOV = (opc_of == 6'o45);
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wire fMTS = fMOV & &imm_of[15:14];
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wire fMTS = fMOV & &imm_of[15:14];
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wire fMOP = fMOV & ~|imm_of[15:14];
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wire fMOP = fMOV & ~|imm_of[15:14];
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wire fMFS = fMOV & imm_of[15] & !imm_of[14];
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reg [31:0] sfr_ex;
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reg [31:0] sfr_ex;
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reg [2:0] sfr_sel;
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_DTE <= 1'h0;
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rMSR_EE <= 1'h0;
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rMSR_EIP <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_ITE <= 1'h0;
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rMSR_MTX <= 1'h0;
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sfr_ex <= 32'h0;
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sfr_ex <= 32'h0;
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sfr_mx <= 32'h0;
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sfr_mx <= 32'h0;
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sfr_sel <= 3'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin // if (grst)
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end else if (dena) begin
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sfr_mx <= #1 sfr_ex;
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case (sfr_sel[2:0])
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//3'o0: sfr_mx <= #1 {rpc_ex[31:2], 2'o0};
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3'o5: sfr_mx <= #1 {30'd0, rESR_C};
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3'o3: sfr_mx <= #1 rEAR_C;
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3'o1: sfr_mx <= #1 {rMSR_C,
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AEMB_HTX[0],
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gpha,
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19'd0,
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rMSR_EIP,
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rMSR_EE,
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rMSR_DTE,
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1'b0,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_BIP,
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rMSR_C,
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rMSR_IE,
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rMSR_BE
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};
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default: sfr_mx <= #1 sfr_ex;
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endcase // case (imm_of[2:0])
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sfr_ex <= #1
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sfr_ex <= #1
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{rMSR_CC,
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{rMSR_CC,
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AEMB_HTX[0],
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AEMB_HTX[0],
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gpha,
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gpha,
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21'd0,
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19'd0,
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rMSR_EIP,
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rMSR_EE,
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rMSR_DTE,
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rMSR_DTE,
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1'b0,
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1'b0,
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rMSR_ITE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_MTX,
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rMSR_BIP,
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rMSR_BIP,
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rMSR_CC,
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rMSR_CC,
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rMSR_IE,
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rMSR_IE,
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rMSR_BE
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rMSR_BE
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};
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};
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sfr_sel <= #1 imm_of[2:0];
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end
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always @(posedge gclk)
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if (grst) begin
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rMSR_BE <= 1'h0;
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rMSR_BIP <= 1'h0;
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rMSR_DTE <= 1'h0;
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rMSR_EE <= 1'h0;
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rMSR_EIP <= 1'h0;
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rMSR_IE <= 1'h0;
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rMSR_ITE <= 1'h0;
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rMSR_MTX <= 1'h0;
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// End of automatics
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end else if (dena) begin // if (grst)
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rMSR_DTE <= #1
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rMSR_DTE <= #1
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(fMTS) ? opa_of[7] :
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(fMTS) ? opa_of[7] :
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(fMOP) ? wRES[7] :
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(fMOP) ? wRES[7] :
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rMSR_DTE;
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rMSR_DTE;
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Line 350... |
(fRTED) ? 1'b0 :
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(fRTED) ? 1'b0 :
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(fMTS) ? opa_of[9] :
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(fMTS) ? opa_of[9] :
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(fMOP) ? wRES[9] :
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(fMOP) ? wRES[9] :
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rMSR_EIP;
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rMSR_EIP;
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/*
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case ({fMTS, fMOP})
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2'o2: {rMSR_DTE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_BE} <= #1 {opa_of[7],
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opa_of[5],
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opa_of[4],
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opa_of[0]};
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2'o1: {rMSR_DTE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_BE} <= #1 {wRES[7],
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wRES[5],
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wRES[4],
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wRES[0]};
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default: {rMSR_DTE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_BE} <= #1 {rMSR_DTE,
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rMSR_ITE,
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rMSR_MTX,
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rMSR_BE};
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endcase // case ({fMTS, fMOP})
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case ({fMTS, fMOP})
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2'o2: {rMSR_BIP,
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rMSR_IE} <= #1 {opa_of[3],
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opa_of[1]};
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2'o1: {rMSR_BIP,
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rMSR_IE} <= #1 {wRES[3],
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wRES[1]};
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default: begin
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rMSR_BIP <= #1 (fBRKB | fRTBD) ? !rMSR_BIP : rMSR_BIP;
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rMSR_IE <= #1 (fBRKI | fRTID) ? !rMSR_IE : rMSR_IE;
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end
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endcase // case ({fMTS, fMOP})
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*/
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end // if (dena)
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end // if (dena)
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// BARREL C
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// BARREL C
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wire fADDSUB = !opc_of[5] & !opc_of[4] & !opc_of[2];
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wire fADDSUB = !opc_of[5] & !opc_of[4] & !opc_of[2];
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// (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
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// (opc_of[5:2] == 4'h0) | (opc_of[5:2] == 4'h2);
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wire fSHIFT = (opc_of == 6'o44) & &imm_of[6:5];
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wire fSHIFT = (opc_of == 6'o44) & &imm_of[6:5];
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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rEAR_C <= 32'h0;
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rESR_C <= 2'h0;
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rMSR_CC <= 1'h0;
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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rEAR_C <= #1 rEAR;
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rESR_C <= #1 rESR;
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rMSR_CC <= #1 rMSR_C;
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//sfr_mx <= #1 sfr_ex;
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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rEAR <= 32'h0;
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rESR <= 2'h0;
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rMSR_C <= 1'h0;
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rMSR_C <= 1'h0;
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rMSR_CC <= 1'h0;
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// End of automatics
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// End of automatics
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end else if (dena) begin
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end else if (dena) begin
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rMSR_CC <= #1 rMSR_C;
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rEAR <= #1 (exc_dwb[1]) ? {mem_ex, 2'o0} : rEAR_C; // LXX/SXX
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rESR <= #1 (exc_ill | exc_dwb[1]) ?
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{exc_ill, exc_dwb[1]} : rESR_C; // ESR
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rMSR_C <= #1
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rMSR_C <= #1
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(fMTS) ? opa_of[2] :
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(fMTS) ? opa_of[2] :
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(fMOP) ? wRES[2] :
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(fMOP) ? wRES[2] :
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(fSHIFT) ? opa_of[0] : // SRA/SRL/SRC
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(fSHIFT) ? opa_of[0] : // SRA/SRL/SRC
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(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
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(fADDSUB) ? add_c : // ADD/SUB/ADDC/SUBC
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rMSR_CC;
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rMSR_CC;
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/*
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end // if (dena)
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case ({fMTS,fMOP,fSHIFT,fADDSUB})
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4'h8: rMSR_C <= #1 opa_of[2];
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4'h4: rMSR_C <= #1 wRES[2];
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4'h2: rMSR_C <= #1 opa_of[0];
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4'h1: rMSR_C <= #1 add_c;
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default: rMSR_C <= #1 rMSR_CC;
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endcase // case ({fMTS,fMOP,fSHIFT,fADDSUB})
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*/
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end
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endmodule // aeMB2_intu
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endmodule // aeMB2_intu
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