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https://opencores.org/ocsvn/aes3rx/aes3rx/trunk
[/] [aes3rx/] [trunk/] [rtl/] [vhdl/] [aes3rx.vhd] - Diff between revs 10 and 11
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| Rev 10 |
Rev 11 |
| Line 345... |
Line 345... |
bsync_int <= z_detected;
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bsync_int <= z_detected;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- Eight bit shift register for preamble detection and decoder functionality.
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bbbr_shift_reg_proc: process (clk)
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begin
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if clk'event and clk = '1' then
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if reset = '1' then
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decoder_shift <= (others => '0');
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elsif aes3_clk = '1' then
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decoder_shift <= aes3_sync(0) & decoder_shift(7 downto 1);
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end if;
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end if;
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end process;
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-- Two consecutive sampled symbols, when equal, are considered as logical 0. Two consecutive sampled
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-- Two consecutive sampled symbols, when equal, are considered as logical 0. Two consecutive sampled
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-- symbols, when differs, are considered as logical 1. This logical value is then shifted into
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-- symbols, when differs, are considered as logical 1. This logical value is then shifted into
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-- data_shift_reg.
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-- data_shift_reg.
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data_shift_reg_proc: process (clk)
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data_shift_reg_proc: process (clk)
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begin
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begin
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