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URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [bench/] [tb.v] - Diff between revs 6 and 7

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Rev 6 Rev 7
Line 1... Line 1... 
`timescale 1ns / 10ps
 
`timescale 1ns / 10ps
 
module tb ();
 
module tb ();
 
 
 
 
 
reg clk;
 
reg clk;
 
reg reset_n;
 
reg reset;
 
reg [7:0] din;
 
reg [7:0] din;
 
wire [7:0] dout;
 
wire [7:0] dout;
 
 
 
 
 
reg key_start;
 
reg key_start;
 
reg [255:0] key_in;
 
reg [255:0] key_in;
Line 17... Line 17... 
begin
 
begin
 
        clk = 1'b1;
 
        clk = 1'b1;
 
        key_in = 1'b0;
 
        key_in = 1'b0;
 
        key_start = 1'b0;
 
        key_start = 1'b0;
 
        data_in_valid = 1'b0;
 
        data_in_valid = 1'b0;
 
        reset_n = 1'b0;
 
        reset = 1'b1;
 
        enable = 1;
 
        enable = 1;
 
        #100;
 
        #100;
 
        reset_n = 1'b1;
 
        reset = 1'b0;
 
        #100;
 
        #100;
 
        din = 8'hae;
 
        din = 8'hae;
 
        @ (posedge clk);
 
        @ (posedge clk);
 
        key_start <= 1'b1;
 
        key_start <= 1'b1;
 
        //key_in[255:128] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
 
        //key_in[255:128] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
Line 81... Line 81... 
//wire [63:0] wr_data;
 
//wire [63:0] wr_data;
 
 
 
 
 
wire [127:0] data_out;
 
wire [127:0] data_out;
 
aes dut(
 
aes dut(
 
   .clk(clk),
 
   .clk(clk),
 
   .reset_n(reset_n),
 
   .reset(reset),
 
   .i_start(key_start),
 
   .i_start(key_start),
 
   .i_enable(enable), //TBD
 
   .i_enable(enable), //TBD
 
   .i_ende(1'b1),
 
   .i_ende(1'b1),
 
   .i_key(key_in),
 
   .i_key(key_in),
 
   .i_key_mode(2'b01),
 
   .i_key_mode(2'b01),

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