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//---------------------------------------------------------------------------------------
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// Project: High Throughput & Low Area AES Core
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//
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// File name: tb_kat.v (Jan 1, 2011)
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//
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// Writer: Moti Litochevski
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//
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// Description:
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// This file contains a basic test bench to demonstrate the core functionality &
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// interfaces including pipelined operation. For each key length the test bench
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// encrypts four plain text vectors using a single key and then decrypts the four
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// cipher text vectors using the same key.
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// The test bench demonstrates the key expansion, encryption and decryption for all
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// three key lengths with pipelined operation.
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//
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// Revision History:
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//
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// Rev <revnumber> <Date> <owner>
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// <comment>
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//
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//---------------------------------------------------------------------------------------
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`timescale 1ns / 10ps
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`timescale 1ns / 10ps
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module tb ();
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module test ();
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reg clk;
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//---------------------------------------------------------------------------------------
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// global signals
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reg clock;
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reg reset;
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reg reset;
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reg [7:0] din;
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wire [7:0] dout;
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// test bench variables
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integer dout_count;
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// UUT interface signals
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reg key_start;
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reg key_start;
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reg enable;
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reg enc_dec;
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reg [255:0] key_in;
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reg [255:0] key_in;
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reg data_in_valid;
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reg [1:0] key_mode;
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reg [127:0] data_in;
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reg [127:0] data_in;
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wire key_ready;
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reg data_in_valid;
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wire ready_out;
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wire ready_out;
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reg enable;
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wire [127:0] data_out;
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wire data_out_valid;
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wire key_ready;
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//---------------------------------------------------------------------------------------
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// test bench implementation
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// global clock generator
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initial clock = 1'b1;
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always #10 clock = ~clock;
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// gloabl reset generator
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initial
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initial
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begin
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begin
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clk = 1'b1;
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key_in = 1'b0;
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key_start = 1'b0;
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data_in_valid = 1'b0;
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reset = 1'b1;
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reset = 1'b1;
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enable = 1;
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#100;
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#100;
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reset = 1'b0;
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reset = 1'b0;
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#100;
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end
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din = 8'hae;
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@ (posedge clk);
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// cosmetics
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initial
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begin
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// announce start of simulation
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$display("");
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$display("-------------------------------------");
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$display(" AES_HT_LA Simulation");
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$display("-------------------------------------");
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$display("");
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// VCD dump
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$dumpfile("test.vcd");
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$dumpvars(0, test);
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$display("");
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end
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// main test bench process control
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initial
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begin
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// default input values
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key_start = 1'b0;
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enable = 1'b1;
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enc_dec = 1'b0;
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key_in = 256'b0;
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key_mode = 2'b0;
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data_in = 128'b0;
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data_in_valid = 1'b0;
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dout_count = 0;
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// wait for reset release
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@(posedge clock);
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wait (~reset);
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@(posedge clock);
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// encryption for 128 bit key mode
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$display("Testing encryption for 128 bit key:");
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$display("-------------------------------------");
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// set core mode to encryption and key size to 128
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enc_dec <= 1'b0;
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key_mode <= 2'b00;
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// set the key value and start key expansion
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key_in[255:128] <= 128'h2b7e151628aed2a6abf7158809cf4f3c;
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key_start <= 1'b1;
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key_start <= 1'b1;
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//key_in[255:128] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
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@(posedge clock);
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//key_in[255:64] = 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b;
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//key_in[255:0] = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
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key_in[255:64] = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
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//key_in[255:0] = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
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@ (posedge clk);
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key_start <= 1'b0;
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key_start <= 1'b0;
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wait (key_ready);
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@(posedge clock);
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// display key value
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$display("Key: 128'h%32h", key_in[255:128]);
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// wait for key expansion to finish
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while (!key_ready) @(posedge clock);
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// announce key expansion ended
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$display("Key expansion done");
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$display("");
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// first plain text input data
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data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
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data_in_valid <= 1'b1;
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data_in_valid <= 1'b1;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731;
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@ (posedge clock);
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//data_in[127:0] = 128'h00112233445566778899aabbccddeeff;
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// display data value
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//data_in[127:0] = 128'h8ea2b7ca516745bfeafc49904b496089;
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$display("Plaintext Data 1: 128'h%32h", data_in);
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data_in[127:0] = 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
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// second plain text input data
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//@ (posedge clk);
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data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734;
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data_in_valid <= 1'b1;
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//@ (posedge clk);
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@ (posedge clock);
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//data_in_valid <= 1'b0;
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// display data value
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370731;
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$display("Plaintext Data 2: 128'h%32h", data_in);
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//@ (posedge clk);
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// third plain text input data
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//data_in_valid <= 1'b1;
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data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;
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//data_in[127:0] = 128'h3243f6a8885a308d313198a2e0370734;
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data_in_valid <= 1'b1;
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//data_in[127:0] = 128'h00112233445566778899aabbccddeeff;
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@ (posedge clock);
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@ (posedge clk);
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// display data value
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data_in_valid <= 1'b0;
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$display("Plaintext Data 3: 128'h%32h", data_in);
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repeat (3) @ (posedge clk);
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// forth plain text input data
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wait (ready_out);
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data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;
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@ (posedge clk);
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data_in_valid <= 1'b1;
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//data_in_valid <= 1'b1;
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@ (posedge clock);
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@ (posedge clk);
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// display data value
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data_in_valid <= 1'b0;
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$display("Plaintext Data 4: 128'h%32h", data_in);
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repeat (6) @(posedge clk);
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// no more data can be given to the core
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//enable <= 0;
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data_in_valid <= 1'b0;
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//repeat (15) @(posedge clk);
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@(posedge clock);
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//enable <= 1;
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#200;
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// announce state
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//$display("dout is %h",dout);
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$display("");
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din = 8'h1e;
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$display("Waiting for cipher text data");
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#2000;
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//$display("dout is %h",dout);
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// wait for all output cipher text data
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#100;
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dout_count = 0;
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$finish;
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while (dout_count < 4)
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begin
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// check for a new output data
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if (data_out_valid)
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dout_count <= dout_count + 1;
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// wait for next clock cycle
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@(posedge clock);
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end
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end
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$display("");
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/*sbox u_sbox(
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// continue with decryption of the same cipher text without key expansion
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.clk(clk),
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$display("Testing decryption for 128 bit key:");
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.reset_n(reset_n),
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$display("-------------------------------------");
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.din(din),
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// set core mode to decryption
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.ende(1'b1),
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enc_dec <= 1'b1;
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.dout(dout));*/
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@(posedge clock);
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//wire wr;
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// display key value
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//wire [4:0] wr_addr;
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$display("Key: 128'h%32h", key_in[255:128]);
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//wire [63:0] wr_data;
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// announce key expansion is not done again
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$display("Using the same key, expansion is not required.");
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$display("");
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wire [127:0] data_out;
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// first cipher text input data
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aes dut(
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data_in[127:0] <= 128'hef0bc156ed8ff21223f247b3e0318a99;
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.clk(clk),
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 1: 128'h%32h", data_in);
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// second cipher text input data
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data_in[127:0] <= 128'hf91914cd01924b124c2ec316b4b35a79;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 2: 128'h%32h", data_in);
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// third cipher text input data
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data_in[127:0] <= 128'h8df4e9aac5c7573a27d8d055d6e4d64b;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 3: 128'h%32h", data_in);
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// forth cipher text input data
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data_in[127:0] <= 128'hec8ce641087165a463d4118dc35f9001;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 4: 128'h%32h", data_in);
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// no more data can be given to the core
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data_in_valid <= 1'b0;
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// announce state
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$display("");
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$display("Waiting for plain text data");
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// wait for all output plain text data
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dout_count = 0;
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while (dout_count < 4)
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begin
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// check for a new output data
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if (data_out_valid)
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dout_count <= dout_count + 1;
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// wait for next clock cycle
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@(posedge clock);
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end
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$display("");
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// encryption for 192 bit key mode
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$display("Testing encryption for 192 bit key:");
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$display("-------------------------------------");
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// set core mode to encryption and key size to 192
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enc_dec <= 1'b0;
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key_mode <= 2'b01;
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// set the key value and start key expansion
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key_in[255:64] <= 192'h8e73b0f7da0e6452c810f32b809079e562f8ead2522c6b7b;
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key_start <= 1'b1;
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@(posedge clock);
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key_start <= 1'b0;
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@(posedge clock);
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// display key value
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$display("Key: 192'h%32h", key_in[255:64]);
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// wait for key expansion to finish
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while (!key_ready) @(posedge clock);
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// announce key expansion ended
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$display("Key expansion done");
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$display("");
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// first plain text input data
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data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Plaintext Data 1: 128'h%32h", data_in);
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// second plain text input data
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data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Plaintext Data 2: 128'h%32h", data_in);
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// third plain text input data
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data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Plaintext Data 3: 128'h%32h", data_in);
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// forth plain text input data
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data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Plaintext Data 4: 128'h%32h", data_in);
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// no more data can be given to the core
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data_in_valid <= 1'b0;
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@(posedge clock);
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// announce state
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$display("");
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$display("Waiting for cipher text data");
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// wait for all output cipher text data
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dout_count = 0;
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while (dout_count < 4)
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begin
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// check for a new output data
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if (data_out_valid)
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dout_count <= dout_count + 1;
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// wait for next clock cycle
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@(posedge clock);
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end
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$display("");
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// continue with decryption of the same cipher text without key expansion
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$display("Testing decryption for 192 bit key:");
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$display("-------------------------------------");
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// set core mode to decryption
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enc_dec <= 1'b1;
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@(posedge clock);
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// display key value
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$display("Key: 192'h%32h", key_in[255:64]);
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// announce key expansion is not done again
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$display("Using the same key, expansion is not required.");
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$display("");
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// first cipher text input data
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data_in[127:0] <= 128'h17d3cbb6a98f64ccd134e0d0b7695aa9;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 1: 128'h%32h", data_in);
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// second cipher text input data
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data_in[127:0] <= 128'h4a7d86377de2a8faf00f8ef97c2eb982;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 2: 128'h%32h", data_in);
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// third cipher text input data
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data_in[127:0] <= 128'heb1b03f2acb64bcf28c9991cc8a4fa50;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 3: 128'h%32h", data_in);
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// forth cipher text input data
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data_in[127:0] <= 128'h2adc503e1c9b669de6b5bc904035547d;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Ciphertext Data 4: 128'h%32h", data_in);
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// no more data can be given to the core
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data_in_valid <= 1'b0;
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// announce state
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$display("");
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$display("Waiting for plain text data");
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// wait for all output plain text data
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dout_count = 0;
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while (dout_count < 4)
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begin
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// check for a new output data
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if (data_out_valid)
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dout_count <= dout_count + 1;
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// wait for next clock cycle
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@(posedge clock);
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end
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$display("");
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// encryption for 256 bit key mode
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$display("Testing encryption for 256 bit key:");
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$display("-------------------------------------");
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// set core mode to encryption and key size to 256
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enc_dec <= 1'b0;
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key_mode <= 2'b10;
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// set the key value and start key expansion
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key_in[255:0] <= 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
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key_start <= 1'b1;
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@(posedge clock);
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key_start <= 1'b0;
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@(posedge clock);
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// display key value
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$display("Key: 256'h%32h", key_in[255:64]);
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// wait for key expansion to finish
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while (!key_ready) @(posedge clock);
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// announce key expansion ended
|
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$display("Key expansion done");
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$display("");
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// first plain text input data
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data_in[127:0] <= 128'hdda97ca4864cdfe06eaf70a0ec0d7191;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Plaintext Data 1: 128'h%32h", data_in);
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// second plain text input data
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data_in[127:0] <= 128'h3243f6a8885a308d313198a2e0370731;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
|
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$display("Plaintext Data 2: 128'h%32h", data_in);
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// third plain text input data
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data_in[127:0] <= 128'h00112233445566778899aabbccddeeff;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
|
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$display("Plaintext Data 3: 128'h%32h", data_in);
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// forth plain text input data
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data_in[127:0] <= 128'h8ea2b7ca516745bfeafc49904b496089;
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data_in_valid <= 1'b1;
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@ (posedge clock);
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// display data value
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$display("Plaintext Data 4: 128'h%32h", data_in);
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// no more data can be given to the core
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data_in_valid <= 1'b0;
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@(posedge clock);
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// announce state
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$display("");
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$display("Waiting for cipher text data");
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// wait for all output cipher text data
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dout_count = 0;
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while (dout_count < 4)
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begin
|
|
// check for a new output data
|
|
if (data_out_valid)
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dout_count <= dout_count + 1;
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// wait for next clock cycle
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@(posedge clock);
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end
|
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$display("");
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|
|
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// continue with decryption of the same cipher text without key expansion
|
|
$display("Testing decryption for 256 bit key:");
|
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$display("-------------------------------------");
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// set core mode to decryption
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enc_dec <= 1'b1;
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@(posedge clock);
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// display key value
|
|
$display("Key: 256'h%32h", key_in[255:0]);
|
|
// announce key expansion is not done again
|
|
$display("Using the same key, expansion is not required.");
|
|
$display("");
|
|
|
|
// first cipher text input data
|
|
data_in[127:0] <= 128'h32573d9003bfd345029779298be53b96;
|
|
data_in_valid <= 1'b1;
|
|
@ (posedge clock);
|
|
// display data value
|
|
$display("Ciphertext Data 1: 128'h%32h", data_in);
|
|
// second cipher text input data
|
|
data_in[127:0] <= 128'ha5f464b57512d05db2bae8d2415b921d;
|
|
data_in_valid <= 1'b1;
|
|
@ (posedge clock);
|
|
// display data value
|
|
$display("Ciphertext Data 2: 128'h%32h", data_in);
|
|
// third cipher text input data
|
|
data_in[127:0] <= 128'hd83414223d20a0c928b136c884d07ea2;
|
|
data_in_valid <= 1'b1;
|
|
@ (posedge clock);
|
|
// display data value
|
|
$display("Ciphertext Data 3: 128'h%32h", data_in);
|
|
// forth cipher text input data
|
|
data_in[127:0] <= 128'hc1f968d2a6859137bd9ad9111ad7f6dc;
|
|
data_in_valid <= 1'b1;
|
|
@ (posedge clock);
|
|
// display data value
|
|
$display("Ciphertext Data 4: 128'h%32h", data_in);
|
|
// no more data can be given to the core
|
|
data_in_valid <= 1'b0;
|
|
|
|
// announce state
|
|
$display("");
|
|
$display("Waiting for plain text data");
|
|
|
|
// wait for all output plain text data
|
|
dout_count = 0;
|
|
while (dout_count < 4)
|
|
begin
|
|
// check for a new output data
|
|
if (data_out_valid)
|
|
dout_count <= dout_count + 1;
|
|
// wait for next clock cycle
|
|
@(posedge clock);
|
|
end
|
|
$display("");
|
|
|
|
// announce simulation end
|
|
$display(" Simulation Done !!!");
|
|
|
|
repeat (10) @(posedge clock);
|
|
$finish;
|
|
end
|
|
|
|
// unit under test
|
|
aes dut
|
|
(
|
|
.clk(clock),
|
.reset(reset),
|
.reset(reset),
|
.i_start(key_start),
|
.i_start(key_start),
|
.i_enable(enable), //TBD
|
.i_enable(enable),
|
.i_ende(1'b1),
|
.i_ende(enc_dec),
|
.i_key(key_in),
|
.i_key(key_in),
|
.i_key_mode(2'b01),
|
.i_key_mode(key_mode),
|
.i_data(data_in),
|
.i_data(data_in),
|
.i_data_valid(data_in_valid),
|
.i_data_valid(data_in_valid),
|
.o_ready(ready_out),
|
.o_ready(ready_out),
|
.o_data(data_out),
|
.o_data(data_out),
|
.o_data_valid(data_out_valid),
|
.o_data_valid(data_out_valid),
|
.o_key_ready(key_ready)
|
.o_key_ready(key_ready)
|
);
|
);
|
|
|
/*key_exp u_key_exp (
|
// display output data from the core
|
.clk(clk),
|
always @ (posedge clock)
|
.reset_n(reset_n),
|
|
.key_in(key_in),
|
|
.key_mode(2'b10),
|
|
.key_start(key_start),
|
|
.wr(wr),
|
|
.wr_addr(wr_addr),
|
|
.wr_data(wr_data)
|
|
);*/
|
|
|
|
always @ (posedge clk)
|
|
if (data_out_valid)
|
if (data_out_valid)
|
$display("DATA: %16h",data_out);
|
$display("Output Data %1d: 128'h%16h", dout_count+1, data_out);
|
|
|
|
|
always
|
|
#10 clk = ~clk;
|
|
|
|
endmodule
|
endmodule
|
|
//---------------------------------------------------------------------------------------
|
|
// Th.. Th.. Th.. Thats all folks !!!
|
|
//---------------------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
