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https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk
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Rev 7 |
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// - Luo Dongjun, dongjun_luo@hotmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// uncomment the following define to enable use of distributed RAM implementation
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// for XILINX FPGAs instead of block memory.
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`define XILINX 1
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module aes (
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module aes (
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clk,
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clk,
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reset,
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reset,
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i_start,
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i_start,
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i_enable,
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i_enable,
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generate
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generate
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for (i=0;i<16;i=i+1)
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for (i=0;i<16;i=i+1)
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begin : sbox_block
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begin : sbox_block
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sbox u_sbox (
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sbox u_sbox (
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.clk(clk),
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.clk(clk),
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.reset_n(~reset),
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.reset(reset),
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.enable(i_enable),
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.enable(i_enable),
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.ende(i_ende),
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.ende(i_ende),
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.din(o_data[i*8+7:i*8]),
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.din(o_data[i*8+7:i*8]),
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.en_dout(en_sb_data[i*8+7:i*8]),
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.en_dout(en_sb_data[i*8+7:i*8]),
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.de_dout(de_sb_data[i*8+7:i*8])
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.de_dout(de_sb_data[i*8+7:i*8])
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/*****************************************************************************/
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/*****************************************************************************/
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// round key generation: the expansion keys are stored in 4 16*32 rams or
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// round key generation: the expansion keys are stored in 4 16*32 rams or
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// 2 16*64 rams or 1 16*128 rams
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// 2 16*64 rams or 1 16*128 rams
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//
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//
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//assign rd_addr[3:0] = i_ende ? (max_round[3:0] - sb_round_cnt2[3:0]) : sb_round_cnt2[3:0];
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//assign rd_addr[3:0] = i_ende ? (max_round[3:0] - sb_round_cnt2[3:0]) : sb_round_cnt2[3:0];
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`define XILINX 1
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assign round_key[127:0] = {rd_data0[63:0],rd_data1[63:0]};
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assign round_key[127:0] = {rd_data0[63:0],rd_data1[63:0]};
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`ifdef XILINX
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`ifdef XILINX
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reg [3:0] rd_addr;
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reg [3:0] rd_addr;
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// Key Expansion module
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// Key Expansion module
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//
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//
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//
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//
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key_exp u_key_exp (
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key_exp u_key_exp (
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.clk(clk),
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.clk(clk),
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.reset_n(~reset),
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.reset(reset),
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.key_in(i_key[255:0]),
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.key_in(i_key[255:0]),
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.key_mode(i_key_mode[1:0]),
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.key_mode(i_key_mode[1:0]),
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.key_start(i_start),
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.key_start(i_start),
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.wr(wr),
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.wr(wr),
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.wr_addr(wr_addr[4:0]),
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.wr_addr(wr_addr[4:0]),
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