| Line 55... |
Line 55... |
// high means the memory access is a read
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// high means the memory access is a read
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// read or write, low for instruction
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// read or write, low for instruction
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output reg [31:0] o_copro_write_data = 'd0,
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output reg [31:0] o_copro_write_data = 'd0,
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output reg [31:0] o_write_data = 'd0,
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output reg [31:0] o_write_data = 'd0,
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output reg [31:0] o_address = 32'hdead_dead,
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output wire [31:0] o_address,
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output reg o_adex = 'd0, // Address Exception
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output reg o_adex = 'd0, // Address Exception
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output reg o_address_valid = 'd0, // Prevents the reset address value being a
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output reg o_address_valid = 'd0, // Prevents the reset address value being a
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// wishbone access
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// wishbone access
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output [31:0] o_address_nxt, // un-registered version of address to the
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output [31:0] o_address_nxt, // un-registered version of address to the
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// cache rams address ports
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// cache rams address ports
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| Line 198... |
Line 198... |
wire [31:0] alu_out_pc_filtered;
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wire [31:0] alu_out_pc_filtered;
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wire adex_nxt;
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wire adex_nxt;
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wire carry_in;
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wire carry_in;
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reg [31:0] address_r = 32'hdead_dead;
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// ========================================================
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// ========================================================
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// Status Bits in PC register
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// Status Bits in PC register
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// ========================================================
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// ========================================================
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assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
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assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
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| Line 262... |
Line 264... |
// ========================================================
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// ========================================================
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// Adders
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// Adders
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// ========================================================
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// ========================================================
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assign pc_plus4 = pc + 32'd4;
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assign pc_plus4 = pc + 32'd4;
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assign pc_minus4 = pc - 32'd4;
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assign pc_minus4 = pc - 32'd4;
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assign address_plus4 = o_address + 32'd4;
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assign address_plus4 = address_r + 32'd4;
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assign alu_plus4 = alu_out + 32'd4;
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assign alu_plus4 = alu_out + 32'd4;
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assign rn_plus4 = rn + 32'd4;
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assign rn_plus4 = rn + 32'd4;
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// ========================================================
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// ========================================================
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// Barrel Shift Amount Select
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// Barrel Shift Amount Select
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// ========================================================
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// ========================================================
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// An immediate shift value of 0 is translated into 32
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// An immediate shift value of 0 is translated into 32
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assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 :
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assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0 :
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| Line 454... |
Line 457... |
o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_exclusive <= exclusive_update ? i_exclusive_exec : o_exclusive;
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o_exclusive <= exclusive_update ? i_exclusive_exec : o_exclusive;
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o_data_access <= data_access_update ? i_data_access_exec : o_data_access;
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o_data_access <= data_access_update ? i_data_access_exec : o_data_access;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_enable <= write_enable_update ? write_enable_nxt : o_write_enable;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_write_data <= write_data_update ? write_data_nxt : o_write_data;
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o_address <= address_update ? o_address_nxt : o_address;
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address_r <= address_update ? o_address_nxt : address_r;
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o_adex <= address_update ? adex_nxt : o_adex;
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o_adex <= address_update ? adex_nxt : o_adex;
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o_address_valid <= address_update ? 1'd1 : o_address_valid;
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o_address_valid <= address_update ? 1'd1 : o_address_valid;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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o_byte_enable <= byte_enable_update ? byte_enable_nxt : o_byte_enable;
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o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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| Line 470... |
Line 473... |
status_bits_mode_rds <= status_bits_mode_rds_nr;
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status_bits_mode_rds <= status_bits_mode_rds_nr;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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end
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end
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assign o_address = address_r;
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// ========================================================
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// ========================================================
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// Instantiate Barrel Shift
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// Instantiate Barrel Shift
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// ========================================================
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// ========================================================
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