| Line 86... |
Line 86... |
input i_exclusive_exec, // swap access
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input i_exclusive_exec, // swap access
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input [3:0] i_rm_sel,
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input [3:0] i_rm_sel,
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input [3:0] i_rds_sel,
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input [3:0] i_rds_sel,
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input [3:0] i_rn_sel,
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input [3:0] i_rn_sel,
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input [3:0] i_rm_sel_nxt,
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input [3:0] i_rds_sel_nxt,
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input [3:0] i_rn_sel_nxt,
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input [1:0] i_barrel_shift_amount_sel,
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input [1:0] i_barrel_shift_amount_sel,
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input [1:0] i_barrel_shift_data_sel,
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input [1:0] i_barrel_shift_data_sel,
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input [1:0] i_barrel_shift_function,
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input [1:0] i_barrel_shift_function,
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input [8:0] i_alu_function,
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input [8:0] i_alu_function,
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input [1:0] i_multiply_function,
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input [1:0] i_multiply_function,
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| Line 100... |
Line 103... |
input [2:0] i_status_bits_sel,
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input [2:0] i_status_bits_sel,
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input [2:0] i_reg_write_sel,
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input [2:0] i_reg_write_sel,
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input i_user_mode_regs_load,
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input i_user_mode_regs_load,
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input i_user_mode_regs_store_nxt,
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input i_user_mode_regs_store_nxt,
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input i_firq_not_user_mode,
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input i_firq_not_user_mode,
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input i_firq_not_user_mode_nxt,
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input i_write_data_wen,
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input i_write_data_wen,
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input i_base_address_wen, // save LDM base address register,
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input i_base_address_wen, // save LDM base address register,
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// in case of data abort
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// in case of data abort
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input i_pc_wen,
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input i_pc_wen,
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input [14:0] i_reg_bank_wen,
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input [14:0] i_reg_bank_wen,
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input [3:0] i_reg_bank_wsel,
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input i_status_bits_flags_wen,
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input i_status_bits_flags_wen,
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input i_status_bits_mode_wen,
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input i_status_bits_mode_wen,
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input i_status_bits_irq_mask_wen,
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input i_status_bits_irq_mask_wen,
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input i_status_bits_firq_mask_wen,
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input i_status_bits_firq_mask_wen,
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input i_copro_write_data_wen
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input i_copro_write_data_wen
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| Line 145... |
Line 150... |
wire barrel_shift_carry;
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wire barrel_shift_carry;
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wire [3:0] status_bits_flags_nxt;
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wire [3:0] status_bits_flags_nxt;
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reg [3:0] status_bits_flags = 'd0;
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reg [3:0] status_bits_flags = 'd0;
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wire [1:0] status_bits_mode_nxt;
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wire [1:0] status_bits_mode_nxt;
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wire [1:0] status_bits_mode_nr;
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reg [1:0] status_bits_mode = SVC;
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reg [1:0] status_bits_mode = SVC;
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// raw rs select
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wire [1:0] status_bits_mode_rds_nxt;
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wire [1:0] status_bits_mode_rds_nr;
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reg [1:0] status_bits_mode_rds;
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// one-hot encoded rs select
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// one-hot encoded rs select
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wire [3:0] status_bits_mode_rds_oh_nxt;
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wire [3:0] status_bits_mode_rds_oh_nxt;
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reg [3:0] status_bits_mode_rds_oh = 1'd1 << OH_SVC;
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reg [3:0] status_bits_mode_rds_oh = 1'd1 << OH_SVC;
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wire status_bits_mode_rds_oh_update;
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wire status_bits_mode_rds_oh_update;
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wire status_bits_irq_mask_nxt;
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wire status_bits_irq_mask_nxt;
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| Line 159... |
Line 169... |
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wire execute; // high when condition execution is true
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wire execute; // high when condition execution is true
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wire [31:0] reg_write_nxt;
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wire [31:0] reg_write_nxt;
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wire pc_wen;
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wire pc_wen;
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wire [14:0] reg_bank_wen;
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wire [14:0] reg_bank_wen;
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wire [3:0] reg_bank_wsel;
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wire [31:0] multiply_out;
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wire [31:0] multiply_out;
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wire [1:0] multiply_flags;
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wire [1:0] multiply_flags;
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reg [31:0] base_address = 'd0; // Saves base address during LDM instruction in
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reg [31:0] base_address = 'd0; // Saves base address during LDM instruction in
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// case of data abort
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// case of data abort
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| Line 216... |
Line 227... |
// status_bits_mode speeds up the critical path from status_bits_mode through the
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// status_bits_mode speeds up the critical path from status_bits_mode through the
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// register_bank, barrel_shifter and alu. It moves a mux needed for the
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// register_bank, barrel_shifter and alu. It moves a mux needed for the
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// i_user_mode_regs_store_nxt signal back into the previous stage -
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// i_user_mode_regs_store_nxt signal back into the previous stage -
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// so its really part of the decode stage even though the logic is right here
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// so its really part of the decode stage even though the logic is right here
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// In addition the signal is one-hot encoded to further speed up the logic
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// In addition the signal is one-hot encoded to further speed up the logic
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// Raw version is also kept for ram-based register bank implementation.
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assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR :
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assign status_bits_mode_rds_nxt = i_user_mode_regs_store_nxt ? OH_USR :
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status_bits_mode_update ? oh_status_bits_mode(status_bits_mode_nxt) :
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status_bits_mode_update ? status_bits_mode_nxt :
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oh_status_bits_mode(status_bits_mode) ;
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status_bits_mode ;
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assign status_bits_mode_rds_oh_nxt = oh_status_bits_mode(status_bits_mode_rds_nxt);
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assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
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assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
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i_status_bits_sel == 3'd1 ? alu_out [27] :
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i_status_bits_sel == 3'd1 ? alu_out [27] :
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i_copro_read_data [27] ;
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i_copro_read_data [27] ;
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| Line 378... |
Line 392... |
assign pc_wen = i_pc_wen || !execute;
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assign pc_wen = i_pc_wen || !execute;
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// only update register bank if current instruction executes
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// only update register bank if current instruction executes
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assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
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assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
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assign reg_bank_wsel = {{4{~execute}} | i_reg_bank_wsel};
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// ========================================================
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// ========================================================
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// Priviledged output flag
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// Priviledged output flag
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// ========================================================
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// ========================================================
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// Need to look at status_bits_mode_nxt so switch to priviledged mode
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// Need to look at status_bits_mode_nxt so switch to priviledged mode
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| Line 414... |
Line 430... |
assign status_bits_mode_update = !i_fetch_stall && execute && i_status_bits_mode_wen;
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assign status_bits_mode_update = !i_fetch_stall && execute && i_status_bits_mode_wen;
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assign status_bits_mode_rds_oh_update = !i_fetch_stall;
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assign status_bits_mode_rds_oh_update = !i_fetch_stall;
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assign status_bits_irq_mask_update = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
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assign status_bits_irq_mask_update = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
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assign status_bits_firq_mask_update = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
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assign status_bits_firq_mask_update = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
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assign status_bits_mode_rds_nr = status_bits_mode_rds_oh_update ? status_bits_mode_rds_nxt :
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status_bits_mode_rds ;
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assign status_bits_mode_nr = status_bits_mode_update ? status_bits_mode_nxt :
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status_bits_mode ;
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always @( posedge i_clk )
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always @( posedge i_clk )
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begin
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begin
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
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o_exclusive <= exclusive_update ? i_exclusive_exec : o_exclusive;
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o_exclusive <= exclusive_update ? i_exclusive_exec : o_exclusive;
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| Line 431... |
Line 452... |
o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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o_copro_write_data <= copro_write_data_update ? write_data_nxt : o_copro_write_data;
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base_address <= base_address_update ? rn : base_address;
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base_address <= base_address_update ? rn : base_address;
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status_bits_flags <= status_bits_flags_update ? status_bits_flags_nxt : status_bits_flags;
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status_bits_flags <= status_bits_flags_update ? status_bits_flags_nxt : status_bits_flags;
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status_bits_mode <= status_bits_mode_update ? status_bits_mode_nxt : status_bits_mode;
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status_bits_mode <= status_bits_mode_nr;
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status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh;
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status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh;
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status_bits_mode_rds <= status_bits_mode_rds_nr;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
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end
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end
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