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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`include "a23_config_defines.v"
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`include "a23_config_defines.vh"
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module a23_execute (
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module a23_execute (
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input i_clk,
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input i_clk,
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input [31:0] i_read_data,
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input [31:0] i_read_data,
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input [2:0] i_status_bits_sel,
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input [2:0] i_status_bits_sel,
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input [2:0] i_reg_write_sel,
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input [2:0] i_reg_write_sel,
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input i_user_mode_regs_load,
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input i_user_mode_regs_load,
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input i_user_mode_regs_store_nxt,
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input i_user_mode_regs_store_nxt,
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input i_firq_not_user_mode,
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input i_firq_not_user_mode,
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input i_firq_not_user_mode_nxt,
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input i_write_data_wen,
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input i_write_data_wen,
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input i_base_address_wen, // save LDM base address register,
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input i_base_address_wen, // save LDM base address register,
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// in case of data abort
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// in case of data abort
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input i_pc_wen,
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input i_pc_wen,
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input i_status_bits_firq_mask_wen,
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input i_status_bits_firq_mask_wen,
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input i_copro_write_data_wen
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input i_copro_write_data_wen
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);
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);
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`include "a23_localparams.v"
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`include "a23_localparams.vh"
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`include "a23_functions.v"
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`include "a23_functions.vh"
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// ========================================================
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// ========================================================
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// Internal signals
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// Internal signals
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// ========================================================
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// ========================================================
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wire [31:0] write_data_nxt;
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wire [31:0] write_data_nxt;
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wire exclusive_update;
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wire exclusive_update;
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wire status_bits_flags_update;
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wire status_bits_flags_update;
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wire status_bits_mode_update;
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wire status_bits_mode_update;
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wire status_bits_irq_mask_update;
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wire status_bits_irq_mask_update;
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wire status_bits_firq_mask_update;
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wire status_bits_firq_mask_update;
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wire [1:0] status_bits_out;
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wire [31:0] alu_out_pc_filtered;
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wire [31:0] alu_out_pc_filtered;
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wire adex_nxt;
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wire adex_nxt;
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// ========================================================
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// ========================================================
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// Status Bits in PC register
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// Status Bits in PC register
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// ========================================================
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// ========================================================
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wire [1:0] status_bits_out;
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assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1 && execute) ?
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assign status_bits_out = (i_status_bits_mode_wen && i_status_bits_sel == 3'd1) ?
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alu_out[1:0] : status_bits_mode ;
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alu_out[1:0] : status_bits_mode ;
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assign o_status_bits = { status_bits_flags, // 31:28
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assign o_status_bits = { status_bits_flags, // 31:28
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status_bits_irq_mask, // 7
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status_bits_irq_mask, // 7
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// Status Bits Select
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// Status Bits Select
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// ========================================================
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// ========================================================
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assign status_bits_flags_nxt = i_status_bits_sel == 3'd0 ? alu_flags :
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assign status_bits_flags_nxt = i_status_bits_sel == 3'd0 ? alu_flags :
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i_status_bits_sel == 3'd1 ? alu_out [31:28] :
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i_status_bits_sel == 3'd1 ? alu_out [31:28] :
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i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] :
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i_status_bits_sel == 3'd3 ? i_copro_read_data[31:28] :
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// 4 = update flags after a multiply operation
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// update flags after a multiply operation
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{ multiply_flags, status_bits_flags[1:0] } ;
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i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :
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// regops that do not change the overflow flag
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i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
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4'b1111 ;
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assign status_bits_mode_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_mode :
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assign status_bits_mode_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_mode :
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i_status_bits_sel == 3'd5 ? i_status_bits_mode :
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i_status_bits_sel == 3'd1 ? alu_out [1:0] :
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i_status_bits_sel == 3'd1 ? alu_out [1:0] :
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i_copro_read_data [1:0] ;
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i_copro_read_data [1:0] ;
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// Used for the Rds output of register_bank - this special version of
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// Used for the Rds output of register_bank - this special version of
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assign status_bits_mode_rds_oh_nxt = oh_status_bits_mode(status_bits_mode_rds_nxt);
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assign status_bits_mode_rds_oh_nxt = oh_status_bits_mode(status_bits_mode_rds_nxt);
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assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
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assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
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i_status_bits_sel == 3'd5 ? i_status_bits_irq_mask :
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i_status_bits_sel == 3'd1 ? alu_out [27] :
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i_status_bits_sel == 3'd1 ? alu_out [27] :
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i_copro_read_data [27] ;
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i_copro_read_data [27] ;
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assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask :
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assign status_bits_firq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_firq_mask :
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i_status_bits_sel == 3'd5 ? i_status_bits_firq_mask :
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i_status_bits_sel == 3'd1 ? alu_out [26] :
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i_status_bits_sel == 3'd1 ? alu_out [26] :
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i_copro_read_data [26] ;
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i_copro_read_data [26] ;
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